Index of /~wimers/files/journals

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]44-Self-Refreshable-Bit-Cell.pdf2023-02-18 08:19 1.0M 
[ ]45-Energy-Efficient-Refreshing.pdf2022-12-31 19:06 1.8M 
[ ]43-Resource-allocation.pdf2021-04-13 06:59 6.6M 
[ ]42-Shielding-Process-Variations.pdf2019-10-31 01:56 1.4M 
[ ]41-Rooted-Trees-Optimization.pdf2019-02-15 16:16 2.0M 
[ ]38-Refreshing-Queue-IEEETC.pdf2018-10-16 08:32 835K 
[ ]39-Shielded-Ring-Oscillator.pdf2018-09-03 06:44 2.2M 
[ ]40-Refreshing-Queue-CAEE.pdf2018-08-28 07:16 1.3M 
[ ]37-Tapering-for-CLK-Tuning.pdf2017-07-28 06:12 1.8M 
[ ]36-MBFF-Design-Optimization.pdf2017-03-31 14:28 2.2M 
[ ]35-Opportunistic-Refresh.pdf2016-11-01 11:46 6.1M 
[ ]31-Power-Supply-Noise-Reduction.pdf2016-08-16 06:34 13M 
[ ]33-Interconnect-Shield-Tapering.pdf2016-08-04 07:27 736K 
[ ]34-Multi-Mode-Addition.pdf2016-06-23 05:52 7.7M 
[ ]32-Weight-Allocation-in-Rooted-Trees.pdf2016-03-13 05:07 1.2M 
[ ]24-VLSI-Layout-Migration.pdf2015-03-28 08:00 2.5M 
[ ]29-DM2-Adder.pdf2015-02-09 15:15 1.9M 
[ ]25-Multi-Layer-Wire-Spacing.pdf2014-11-03 11:04 2.3M 
[ ]28-Hybrid-Adder.pdf2014-11-03 00:12 1.3M 
[ ]30-Covering-and-Clock-Gating.pdf2014-09-23 12:26 675K 
[ ]27-MBFF-Matching-and-Covering.pdf2014-06-21 07:44 458K 
[ ]26-Dual-Mode-Adder.pdf2014-06-11 06:52 1.9M 
[ ]22-Look-Ahead-Gating.pdf2014-04-29 07:07 1.5M 
[ ]20-Optimal-FF-Grouping.pdf2014-03-20 04:12 834K 
[ ]23-Cell-Based-Interconnect-Migration.pdf2014-01-04 08:17 2.9M 
[ ]19-Planar-To-Fin.pdf2013-11-19 05:47 4.7M 
[ ]21-NP-hardness-FF-Grouping.pdf2013-09-03 17:44 709K 
[ ]18-Adaptive-Clock-Gating.pdf2012-09-05 18:58 1.5M 
[ ]17-PwrDlyComplexity.pdf2012-02-07 11:14 3.9M 
[ ]16-Well-Solvable-QAP-for-Interconnect.pdf2012-01-21 09:26 1.0M 
[ ]14-LOP-and-VLSI-Interconnects.pdf2011-10-16 05:39 332K 
[ ]15-Wiener-Max-QAP.pdf2011-07-07 14:21 378K 
[ ]13-DynProgWireSize.pdf2010-09-30 18:23 417K 
[ ]12-PowerDelayOpt.pdf2009-08-31 03:56 3.5M 
[ ]11-OptimalOrderingPower.pdf2008-10-12 14:13 3.0M 
[ ]01-CMOScellOptimalCahining.pdf2007-12-24 15:38 1.3M 
[ ]05-CMOScellDepthFirst.pdf2007-12-24 15:35 722K 
[ ]06-BalancedBlock.pdf2007-12-24 09:21 1.2M 
[ ]07-PathAverage.pdf2007-12-24 09:20 1.0M 
[ ]02-ConstructiveBlock.pdf2007-12-20 16:09 706K 
[ ]04-OptimalAspectRatio.pdf2007-12-20 16:06 776K 
[ ]03-FloorplanPlanarLayout.pdf2007-12-20 15:45 1.2M 
[ ]08-RowCell.pdf2007-12-20 15:36 566K 
[ ]09-OptimalSizing.pdf2007-12-12 12:50 678K 
[ ]10-OptimalOrderingTiming.pdf2007-12-12 12:46 939K