Hebrew Name: מבוא למעגלים משולבים ווי.אל.אס.איי

Course Number: 83-313

• English YouTube Playlist of Recorded Lectures (2020)
• Hebrew YouTube Playlist of Recorded Lectures (2017)

1. Introduction, Digital Design
   • English (Slides)
     • Section 1a: Intro to the Intro
     • Section 1b: The World of Chip Design
     • Section 1c: How a Chip is Born
   • Hebrew (Slides, Section 1a-b, Section 1c)
   • Accompanying Kahoot! for Lecture 1
2. The Manufacturing Process
   • English (Slides)
     • Section 2a: A Process Primer
     • Section 2b: Detailed Process Flow
     • Section 2c: Process Variations
     • Section 2d: Manufacturing Issues
   • Hebrew (Slides, Section 2a, Section 2b, Section 2c, Section 2d)
   • Accompanying Kahoot! for Lecture 2
3. MOSFET Modeling
   • English (Slides)
     • Section 3a-3b: MOS Models
     • Section 3c: Threshold Voltage Revisited
     • Section 3d: Simulating Variation
     • Section 3e: Leakage in NanoScaled Transistors
   • Hebrew (Slides, Section 3a, Section 3b, Section 3c, Section 3d, Section 3e)
   • Accompanying Kahoot! for Lecture 3 - Sections a-d
   • Accompanying Kahoot! for Lecture 3 - Sections e
4. Design Metrics
   • English (Slides, Video)
   • Hebrew (Slides, Section 4a, Section 4b, Section 4c)
   • Accompanying Kahoot! for Lecture 4
5. Scaling and The NanoScaled MOSFET
   • English (Slides)
     • Section 5a: Moore's Law
     • Section 5b: Scaling Models
     • Section 5c: The NanoScaled Transistor
     • Section 5d: Current and Future Trends
   • Hebrew:
     • Scaling (Slides , Section 5a, Section 5b)
     • The NanoScaled MOSFET (Slides, Section 5c, Section 5d)
   • Accompanying Kahoot! for Lecture 5
6. Interconnect
   • English (Slides)
     • Section 6a-b: Capacitance
     • Section 6c-d: Resistance and Interconnect Modeling
     • Section 6e: Wire Scaling
   • Hebrew (Slides, Section 6a, Section 6b, Section 6c, Section 6d, Section 6e)
   • Accompanying Kahoot! for Lecture 6
7. Sequential Logic
   • English (Slides)
     • Section 7a: Sequential Logic - Motivation
     • Section 7b: Sequential Logic Elements
     • Section 7c: Timing Parameters
     • Section 7d: Other Flip Flop Implementations
     • Section 7e: Basic Timing Constraints
     • Section 7f: Static Timing Analysis Example
   • Hebrew (Slides, Section 7a, Section 7b, Section 7c, Section 7d, Section 7e, Section 7f)
   • Accompanying Kahoot! for Lecture 7
8. SRAM
   • English (Slides)
     • VLSI - Lecture 8a: SRAM - Introduction
     • VLSI - Lecture 8b: The 6T SRAM Bitcell
     • VLSI - Lecture 8c: 6T SRAM Operation
     • VLSI - Lecture 8d: 6T SRAM Layout
     • VLSI - Lecture 8e: SRAM Stability
     • VLSI - Lecture 8f: SNM Calculation
   • Hebrew (Slides, Section 8a, Section 8b and 8d, Section 8c, Section 8e, Section 8f)
   • Accompanying Kahoot! for Lecture 8
9. Memory Peripherals
   • English (Slides)
     • VLSI - Lecture 9a: SRAM Peripherals - Overview
     • VLSI - Lecture 9b: Row Decoder Design
     • VLSI - Lecture 9c: Column Decoder and Sense Amplifiers
   • Hebrew (Slides, Section 9a, Section 9b, Section 9c)
   • Accompanying Kahoot! for Lecture 9
10. Arithmetic Circuits
    • English (Slides)
      • VLSI - Lecture 10a: Arithmetic Circuits - Basic Addition
      • VLSI - Lecture 10b: Fast Adders
      • VLSI - Lecture 10c: Basic Multiplication
      • VLSI - Lecture 10d-e: Fast Multipliers
    • Hebrew (Slides, Section 10a, Section 10b, Section 10c, Section 10d, Section 10e)
    • Accompanying Kahoot! for Lecture 10(a-b)
    • Accompanying Kahoot! for Lecture 10(c-e)
11. Other Memories
    • English (Slides)
      • VLSI - Lecture 11a: Other Memories
      • VLSI - Lecture 11b: Read Only Memory (ROM)
      • VLSI - Lecture 11c: Dynamic RAM (DRAM) 
      • VLSI - Lecture 11d: Non-Volatile Memory (NVM)
      • VLSI - Lecture 11e: Emerging Memories (PCM, ReRAM, MRAM, FeRAM)
    • Hebrew (Slides, Video)
    • Accompanying Kahoot! for Lecture 11

Additional Related Lectures

Advanced Process Nodes

• Slides (English Only)
• Video recordings:

• • Part 1: Moving to the Third Dimension
  • Part 2: Fabricating FinFETs
  • Part 3: FinFET Layout
  • Part 4: Layout Dependent Effects and Parasitics
  • Part 5: Some Current Trends

Behind the Scenes of the SPICE Circuit Simulator

• Slides (English Only)
• Video recordings:

• • Part 1: Introduction
  • Part 2: DC Analysis
  • Part 3: The Newton-Raphson Method
  • Part 4: AC Analysis, Transient Analysis
  • Part 5: Other Stuff

Technology and Standard Cell Layout

• • Hebrew (Slides, Section 12a, Section 12b, Section 12c)