Conferences

Peer-reviewed Conference Proceedings:

  1. E. Garzon, R. De Rosea, F. Crupia, L. Trojmanc, A. Teman and M. Lanuzza, "Relaxing Non-Volatility for Energy-Efficient DMTJ Based Cryogenic STT-MRAM", in Insulating Films on Semiconductors (INFOS), pp. 2021
  2. A. Avnon, R. Golman, E. Garzon, H.-D. Ngo, M. Lanuzza and A. Teman, "Quantum Capacitance Transient Phenomena in High-K dielectric Armchair Graphene Nanoribbon Field-Effect Transistor Model", in Insulating Films on Semiconductors (INFOS), pp., 2021
  3. E. Levy, A. Sfez, R. Golman, O. Harel and A. Teman, "4T Gain-Cell Providing Unlimited Availability Through Hidden Refresh with 1W1R Functionality", in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), pp, May 2021
  4. Y. Kra, T. Noy and A. Teman, "WavePro 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining" in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), DATE 2021, pp. ,2021
  5. Y. Kra, T. Noy and A. Teman, "WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation," 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, pp. 1291-1294
  6. RR. Golman, R. Giterman, O. Harel and A. Teman, "Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5
  7. A. Bonetti, R. Golman, R. Giterman, A. Teman and A. Burg, "Gain-Cell Embedded DRAMs: Modeling and Design Space" in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2020
  8. R. Giterman, A. Bonetti, A. Burg and A. Teman, "GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI," in IEEE Transactions on Circuits and Systems (ISCAS) II: Express Briefs, vol. 66, no. 12, pp. 2042-2046, Dec. 2019
  9. A. Shalom, A. Fish and A. Teman, "A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI," 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019, pp. 1-2
  10. T. Munk, H. Kugler, O. Maori and A. Teman, "TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches," 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT),pp. 1-4, Hsinchu, Taiwan, 2019
  11. O. Maltabashi, H. Marinberg, R. Giterman and A. Teman, "A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, Florence, 2018
  12. A. Bonetti, J. Constantin, A. Teman and A. Burg, "A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, Florence, 2018
  13. R. Giterman, A. Fish, A. Burg and A. Teman, "A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI," in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018.
  14. A. Bonetti, A. Teman, P. Flatresse and A. Burg, "Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters," in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018
  15. R. Golman, R. Giterman and A. Teman, "A Dual-Negative Word-Line Technique for Improving Read Access in GC-eDRAM Arrays," in Proc. of the IEEE Int. Conf. on the Science of Electrical Engineering (ICSEE), December 2018
  16. A. Shalom, R. Giterman and A. Teman, "High Density GC-eDRAM Design in 16nm FinFET," 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 585-588, Bordeaux, December 2018
  17. R. Golman, R. Giterman and A. Teman, "Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism," 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 589-592, Bordeaux, December 2018
  18. R. Giterman, A. Teman and A. Fish, "A 14.3pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI," 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2 Burlingame, CA, USA, Oct. 2018
  19. R. Giterman, R. Golman, A. Shalom, O. Maltabashi, A. Fish and A. Teman, "Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-1, Florence, May 2018
  20. R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, "An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications," ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, pp. 308-311,  Leuven, Sept. 2017
  21. R. Giterman, A. Teman and A. Fish, "A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI," 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-3, San Francisco, CA, 2017
  22. R. Giterman, A. Teman and P. Meinerzhagen, “Highly Configurable Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2017
  23. J. Constantin, A. Bonetti, A. Teman, C. Mueller, L. Schmid, and A. Burg, “DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment,”in  ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, pp. 261-264, Lausanne, September 2016
  24. D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak, A. Teman, et al., “193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-Efficient Parallel and Sequential Digital Processing,” in  2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), pp. 1-3, Yokohama, April 2016
  25. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg, and A. Fish, “A process compensated gain cell embedded DRAM for ultra low power variation aware design,” in  2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1006-1009, Montreal, QC, 2016
  26. R. Ghanaatian, P. Whatmough, J. Constantin, A. Teman and A. Burg, “A low-power correlator for wake-up receivers with algorithm pruning through early termination,” in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2667-2670,  Montreal, QC, May 2016
  27. R. Giterman, A. Teman, L. Atias, and A. Fish, “A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications,” in Proc. of IEEE S3S , pp. 1-2, October 2015
  28. S. Ganapathy, G. Karakonstantis, A. Teman and A. Burg, “Mitigating the impact of faults in unreliable memories for error-resilient applications,” in Proc. of the Design Automation Conference (DAC) DAC, pp. 102:1-106:6, ACM, NY., USA,  2015
  29. S. Ganapathy, A. Teman, R. Giterman, A. P. Burg and G. Karakonstantis, “Approximate computing with unreliable dynamic memories,” in Proc. of Int. New Circuits And Systems Conference (NEWCAS), pp. 1-4, June 2015 Special session on Approximate Computing.
  30. A. Bonetti, A. Teman, and A. P. Burg, “An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2015
  31. A. Teman, G. Karakonstantis, R. Giterman, P. Meinerzhagen and A. Burg, “Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories,” in Proc. of the Design Automation and Test in Europe Conference Exhibition (DATE), DATE 2015, pp. 489–494, San Jose, CA, USA, 2015
  32. A. Teman, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, “Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI,” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC) , pp. 81–86, 2015
  33. L. Atias, A. Teman and A. Fish, "Single event upset mitigation in low power SRAM design," 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), pp. 1-5, Eilat, 2014
  34. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and A. Fish, “4T gain-cell with internal-feedback for ultra-low retention power at scaled CMOS nodes,”in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2177-2180, Melbourne VIC, 2014
  35. A. Teman, “Dynamic Stability and Noise Margins of SRAM Arrays in Nanoscaled Technologies,” in IEEE FTFC 2014, pp. 1-5, Monte Carlo, Monaco
  36. A. Vaknin, O. Yona and A. Teman, "A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation," 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2, Monterey, CA, 2013
  37. L. Atias, A. Teman and A. Fish, "A 13T radiation hardened SRAM bitcell for low-voltage operation," 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2, Monterey, CA, 2013
  38. N. Edri, S. Fraiman, A. Teman and A. Fish, "Data retention voltage detection for minimizing the standby power of SRAM arrays," 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, Eilat, 2012
  39. A. Teman, P. Meinerzhagen, A. Burg and A. Fish, "Review and classification of gain cell eDRAM implementations," 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, Eilat, 2012
  40. P. Meinerzhagen, A. Teman, A. Mordakhay, A. Burg and A. Fish, "A sub-VT 2T gain-cell memory for biomedical applications," 2012 IEEE Subthreshold Microelectronics Conference (SubVT), pp. 1-3, Waltham, MA, 2012
  41. H. Dagan, A. Teman, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, "A low-cost low-power non-volatile memory for RFID applications," 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1827-1830, Seoul, 2012
  42. H. Dagan, A. Teman, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, "A GIDL free tunneling gate driver for a low power non-volatile memory array," 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 452-455, Seoul, 2012
  43. J. Mezhibovsky, A. Teman and A. Fish, "State space modeling for sub-threshold SRAM stability analysis," 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1823-1826, Seoul, 2012
  44. I. Schwartz, A. Teman, R. Dobkin and A. Fish, "Near-threshold 40nm Supply Feedback C-element," 2011 3rd Asia Symposium on Quality Electronic Design (ASQED), pp. 74-78, Kuala Lumpur, 2011
  45. J. Mezhibovsky, A. Teman and A. Fish, "Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM," 2011 IEEE International SOC Conference, pp. 136-141, Taipei, 2011
  46. A. Teman and A. Fish, "Sub-threshold and near-threshold SRAM design," 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel, pp. 000608-000612, Eilat, 2010
  47. A. Teman, O. Yadid-Pecht and A. Fish, "An Improved AB2C scheme for leakage power reduction in image sensors with on-chip memory," SENSORS, 2009 IEEE, pp. 193-196, Christchurch, 2009
  48. S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, "Ultra-low power subthreshold flip-flop design," 2009 IEEE International Symposium on Circuits and Systems, pp. 1573-1576, Taipei, 2009
  49. S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, "Digital subthreshold logic design - motivation and challenges," 2008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel, pp. 702-706 , Eilat, 2008
  50. A. Teman, S. Fisher, L. Sudakov, A. Fish and O. Yadid-Pecht, "Autonomous CMOS image sensor for real time target detection and tracking," 2008 IEEE International Symposium on Circuits and Systems, pp. 2138-2141, Seattle, WA, 2008

Select Talks

  1. O. Maltabashi and A. Teman, "Controlled Placement of Standard Cell Memories with Innovus Implementation System", in CDNLive Israel, October 2017
  2. A. Teman, "FD-SOI Standard Cell Characterization with Cadence Liberate", in CDNLive Israel, October 2016
  3. A. Bonetti, N. Preyss, A. Burg, and A. Teman, “Dual-edge triggered clocking - how we can use it and when,” in CDNLive Israel, October 2015
  4. A. Bonetti, N. Preyss, A. Teman and A. Burg, “Automated Integration of Dual-Edge Triggered Clocking Into the Standard Design Flow ,” in CDNLive EDMA, April 2015
  5. A. Bonetti, J. Constantin, A. Teman and A. Burg, “Circuits and techniques for dynamic timing monitoring in microprocessors,” in Nanotera Annual Meeting 2015, May 2015
  6. A. Teman, G. Karakonstatis, S. Ganapathy, and A. Burg, “Exploiting application error resilience for energy savings in memories,” in Workshop on Approximate Computing (WAPCO), January 2015
  7. A. Teman and A. Fish, “SRAM stability in the nanoscale era,” in CDNLive Israel, September 2012
  8. A. Teman and A. Fish, “Low voltage logic and SRAM design,” in ChipEx 2011, May 2011