Journal Articles:

  1. E. Garzon, R. De Rose, F. Crupi, A. Teman and M. Lanuzza, "Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications", IEEE Transactions on Nanotechnology, vol. 20, pp. 123-128, 2021
  2. R. Giterman, A. Shalom, A. Burg, A. Fish and  A. Teman - "A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET", in IEEE Solid-State Circuits Letters, vol. 3, pp. 110-113, 2020
  3. T. Noy and A. Teman, "Design of a Refresh-Controller for GC-eDRAM Based FIFOs" in  IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4804-4817, Dec. 2020
  4. A. Haran, E. Keren, D. David, N. Refaeli, R. Giterman, M. Assaf, L. Atias, A. Teman and A. Fish, "Single Event Upset Tolerance Study of a Low Voltage 13T Radiation-Hardened SRAM Bitcell," in IEEE Transactions on Nuclear Science, pp. 1-12, 2020
  5. O. Harel, Y. Nachum and R. Giterman, “Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM” in Microelectronics Journal, vol. 101, July 2020
  6. D. Vana, P.E. Gaillardon and A. Teman, "C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors", IEEE Transactions on Nanotechnology, vol. 19, pp. 123-136, Jan. 2020
  7. R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, A. Teman and A. Burg, "Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 4, pp. 1207-1217, April 2020
  8. A. Bonetti, R. Golman, R. Giterman, A. Teman and A. Burg, "Gain-Cell Embedded DRAMs: Modeling and Design Space", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 646-659, March 2020
  9. O. Maltabashi, Y. Kra and A. Teman, "Physically-aware Affinity-driven Multiplier Implementation", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2019
  10. R. Giterman, A. Bonetti, A. Burg and A. Teman, "GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 12, pp. 2042-2046, Dec. 2019
  11. R. Giterman, R. Golman and A. Teman, "Improving energy-efficiency in dynamic memories through retention failure detection," in IEEE Access, vol. 7, pp. 27641-27649, 2019
  12. R. Giterman, Y. Weizman and A. Teman, "Gain-Cell Embedded DRAM Based Physical Unclonable Function," in IEEE trans. Circuits Syst. I, vol. 65, pp. 4208-4218, Dec 2018
  13. R. Giterman, A. Fish, A. Burg and A. Teman, "A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With over 1.6-ms Retention Time at 700 mV in  28-nm FD-SOI," in IEEE Trans. Circuits Syst. I, vol. 65, pp. 1245-1256, April 2018
  14. R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, "An 800MHz Mixed-VT 4T IFGC Embedded DRAM in 28nm CMOS Bulk Process for Approximate Storage Applications", in IEEE J. Solid Circuits, vol. 53, pp. 2136-2148, July 2018
  15. R. Ghanaatian, A. Balatsoukas-Stimming, C. Muller, M. Meidlinger, G. Matz, A. Teman and A. Burg, "A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing," in IEEE Trans. VLSI Syst., vol. 26, pp. 329-340, Feb 2018
  16. R. Giterman, A. Teman and P. Meinerzhagen, "Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation", in IEEE trans. Circuits Syst. II, vol. 64, pp. 1362-1366, Dec 2017
  17. A. Bonetti, A. Teman, P. Flatresse and A. Burg, "Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2388-2400, September 2017
  18. A. Kazimirsky, A. Teman, N. Edri and  A. Fish, "An 0.65V 500MHz Integrated Dynamic and Static RAM (iD-SRAM) for Error Tolerant Applications" in IEEE trans. Circuits Syst. , vol. 25, no. 9, pp. 2411-2418, September 2017
  19. D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Kagan Gurkaynak, A. Teman, et al., Energy Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster,”  in IEEE Micro, vol. 37, pp. 20-31, September 2017
  20. A. Bonetti, N. Preyss, A. Teman and A. Burg, Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes,” in ACM Trans. on Design Automation of Elec. Systems, vol. 22, pp. 62:1-62:20, May 2017
  21. R. Giterman, L. Atias and A. Teman, “Area and energy-efficient complementary dual-modular redundancy dynamic memory for space applications,”  in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 502-509, Feb. 2017
  22. L. Moyal, I. Levi, A. Teman and A. Fish, “Synthesis of dual mode logic,” in Integration - The VLSI Journal (VLSI-D), vol. 55, pp. 246–253, 2016
  23. A. Teman, D. Rossi, P. Meinerzhagen, L. Benini and A. Burg, “Power, area, and performance optimization of standard cell memory arrays through controlled placement,” in ACM TODAES, vol. 21, pp. 59:1–59:25, May 2016
  24. L. Atias, A. Teman, R. Giterman, P. Meinerzhagen and A. Fish, “A low-voltage 13T radiation hardened SRAM bitcell for low-voltage operation,” in IEEETVLSI, vol. 24, no. 8, pp. 2622–2633, 2016
  25. N. Edri, P. Meinerzhagen, A. Teman, A. Burg and A. Fish, “Silicon-proven per-cell retention time distribution model of gain-cell based eDRAM,” in IEEE TCAS-I, vol. 63, pp. 222–232, Feb 2016
  26. R. Giterman, A. Teman, P. Meinerzhagen, L. Atias, A. Burg and A. Fish, “Single-supply 3T gain-cell for low-voltage low-power applications,” in IEEE TVLSI, vol. 24, no. 1, pp. 358–362, 2016
  27. A. Teman and R. Visotsky, “A fast modular method for true variation-aware separatrix tracing in nanoscaled SRAMs,” in IEEE TVLSI, vol. 23, no. 10, pp. 2034–2042, 2015
  28. H. Dagan, A. Shapira, A. Teman, A. Mordakhay, S. Jameson, E. Pikhay, V. Dayan, Y. Roizin, E. Socher, and A. Fish, “A low-power low-cost 24 GHz RFID tag with a C-Flash based embedded memory,” in  IEEE JSSC, vol. 49, no. 9, pp. 1942–1957, 2014
  29. A. Teman, P. Meinerzhagen, R. Giterman, A. Fish, and A. Burg, “Replica technique for adaptive refresh timing of gain-cell-embedded DRAM,” in IEEE TCAS-II, vol. 61, no. 4, pp. 259–263, 2014
  30. P. Meinerzhagen, A. Teman, A. Fish and A. Burg, "Impact of body biasing on the retention time of gain-cell memories," in The Journal Of Engineering, vol. 1, no. 1, 2013
  31. P. Meinerzhagen, A. Teman, R. Giterman, A. Burg and A. Fish, “Exploration of sub-VT and near-VT 2T gain-cell memories for ultra-low power applications under technology scaling,” in MDPI JLPEA, vol. 3, no. 2, pp. 54–72, 2013
  32. H. Dagan, A. Teman, E. Pikhay, V. Dayan, A. Mordakhay, Y. Roizin and A. Fish, “A low-power DCVSL-like GIDL-free voltage driver for low-cost RFID nonvolatile memory,IEEE JSSC, vol. 4, no. 6, pp. 1497–1510, 2013
  33. A. Teman, A. Mordakhay, and A. Fish, “Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell,” in Microelectronics Journal, vol. 44, no. 3, pp. 236–247, 2013
  34. A. Teman, H. Dagan, V. Dayan, E. Pikhay, Y. Roizin, and A. Fish, "Zero-cost ultra-low power non-volatile memory module for RFID applications," Tower Jazz Technical Journal, vol. 4, pp. 46-49, July 2013
  35. A. Spivak, A. Teman, A. Belenky, O. Yadid-Pecht and A. Fish, “Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel,” in MDPI Sensors, vol. 12, no. 8, pp. 10067–10085, 2012
  36. A. Teman, O. Yadid-Pecht and A. Fish, “Leakage reduction in advanced image sensors using an improved AB2C scheme,” in IEEE Sensors Journal, vol. 12, no. 4, pp. 773–784, 2012
  37. A. Teman, A. Mordakhay, J. Mezhibovsky and A. Fish, “A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability,” in IEEE TCAS-II, vol. 59, no. 12, pp. 873–877, 2012
  38. A. Spivak, A. Teman, A. Belenky, O. Yadid-Pecht and A. Fish, "Power-performance tradeoffs in wide dynamic range image sensors with multiple reset approach," in MDPI J. Low Power Elec. and App., vol. 1, no. 1, pp. 59-76, 2011
  39. A. Teman, L. Pergament, O. Cohen and A. Fish, "A minimum leakage quasi-static RAM bitcell," in MDPI J. Low Power Elec. and App., vol.1, no. 1, pp. 204-218, 2011
  40. A. Teman, L. Pergament, O. Cohen and A. Fish, “A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM),” in IEEE JSSC, vol. 46, no. 11, pp. 2713–2726, 2011
  41. A. Teman, O. Yadid-Pecht, and A. Fish, "Large VLSI arrays - power and architectural perspectives" International Journal of Information Technologies and Knowledge (IJ ITK), vol. 4, no. 1, pp. 76-90, 2010