#### Books and Book Chapters:

- P. Meinerzhagen, A. Teman, R. Giterman, N. Edri, A. Burg and
**A. Fish**- “Gain-Cell Embedded DRAMs for Low Power VLSI Systems-on-Chip”, Springer International Publishing, 2018.

#### Journal Articles:

- R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, A. Teman and A. Burg, "Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space," in
*IEEE Transactions on Circuits and Systems I: Regular Papers*, vol. 67, no. 4, pp. 1207-1217, April 2020 - D. Vana, p.E. Gaillardon and
**A.Teman**, "Jan. 2020**C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors**", IEEE Transactions on Nanotechnology, vol. 19, pp. 123-136, - A. Bonetti, R. Golman, R. Giterman,
**A. Teman**and A. Burg, "March 2020**Gain-Cell Embedded DRAMs: Modeling and Design Space**", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 646-659, - O. Maltabashi, Y. Kra and
**A. Teman**, "2019**Physically-aware Affinity-driven Multiplier Implementation**", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, - R. Giterman, A. Bonetti, A. Burg,
**A. Teman**,*"***GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI**,"*IEEE Transactions on Circuits and Systems II: Express Briefs*, vol. 66, no. 12, pp. 2042-2046, Dec. 2019 - R. Giterman, R. Golman, and
**A. Teman**,*"***Improving energy-efficiency in dynamic memories through retention failure detection**,"*IEEE Access*, vol. 7, pp. 27641-27649, 2019 - R. Giterman, Y. Weizman, and
**A. Teman**,*"*, vol. 65, pp. 4208-4218, Dec 2018.**Gain-Cell Embedded DRAM Based Physical Unclonable Function**," IEEE trans. Circuits Syst. I - R. Giterman, A. Fish, A. Burg, and
**A. Teman**,*"*"*A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI*,*IEEE Trans. Circuits Syst. I*, vol. 65, pp. 1245-1256, April 2018. - R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg, and
**A. Teman**,*"*,**An 800MHz Mixed-VT 4T IFGC Embedded DRAM in 28nm CMOS Bulk Process for Approximate Storage Applications**"*IEEE J. Solid Circuits*, vol. 53, pp. 2136-2148, July 2018. - R. Ghanaatian, A. Balatsoukas-Stimming, C. Muller, M. Meidlinger, G. Matz,
**A. Teman**, and A. Burg,*"***A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing**,"*IEEE Trans*.*VLSI Syst*., vol. 26, pp. 329-340, Feb 2018. - R. Giterman,
**A. Teman**and P. Meinerzhagen, "",**Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation***IEEE trans. Circuits Syst. II, vol. 64, pp. 1362-1366, Dec 2017.* - A. Kazimirsky,
**A. Teman**, N. Edri, A. Fish**"An 0.65V 500MHz Integrated Dynamic and Static RAM (iD-SRAM) for Error Tolerant Applications"**IEEE trans. Circuits Syst. , vol. 25, no. 9, pp. 2411-2418, Sep. 2017. - A. Bonetti,
**A. Teman**, P. Flatresse, A. Burg,Accepted to IEEE TCAS-I, 2017.*"Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters"* - A. Bonetti, N. Preyss,
**A. Teman**, A. Burg,Accepted to ACM TODAES, 2017.**“Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes,”** - D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak,
**A. Teman**, et al.,Accepted to IEEE Micro, 2017.*“Energy Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster,”* - R. Giterman, L. Atias, and
**A. Teman**, “,” IEEE TVLSI, vol. PP, no. 99, pp. 1–8, 2016*Area and energy-eﬃcient complementary dual-modular redundancy dynamic memory for space applications* - L. Moyal, I. Levi,
**A. Teman**, and A. Fish, “,” Integration the VLSI Journal (VLSI-D), vol. 55, pp. 246–253, 2016*Synthesis of dual mode logic* **A. Teman**, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, “,” ACM TODAES, vol. 21, pp. 59:1–59:25, May 2016*Power, area, and performance optimization of standard cell memory arrays through controlled placement*- L. Atias,
**A. Teman**, R. Giterman, P. Meinerzhagen, and A. Fish, “,” IEEETVLSI, vol. 24, no. 8, pp. 2622–2633, 2016*A low-voltage 13T radiation hardened SRAM bitcell for low-voltage operation* - N. Edri, P. Meinerzhagen,
**A. Teman**, A. Burg, and A. Fish, “,” IEEE TCAS-I, vol. 63, pp. 222–232, Feb 2016*Silicon-proven per-cell retention time distribution model of gain-cell based eDRAM* - R. Giterman,
**A. Teman**, P. Meinerzhagen, L. Atias, A. Burg, and A. Fish, “,”*Single-supply 3T gain-cell for low-voltage low-power applications**IEEE TVLSI*, vol. 24, no. 1, pp. 358–362, 2016 **A. Teman**and R. Visotsky, “,”*A fast modular method for true variation-aware separatrix tracing in nanoscaled SRAMs**IEEE TVLSI*, vol. 23, no. 10, pp. 2034–2042, 2015- H. Dagan, A. Shapira,
**A. Teman**, A. Mordakhay, S. Jameson, E. Pikhay, V. Dayan, Y. Roizin, E. Socher, and A. Fish, “,”*A low-power low-cost 24 GHz RFID tag with a C-Flash based embedded memory**IEEE JSSC*, vol. 49, no. 9, pp. 1942–1957, 2014 **A. Teman**, P. Meinerzhagen, R. Giterman, A. Fish, and A. Burg, “,”*Replica technique for adaptive refresh timing of gain-cell-embedded DRAM**IEEE TCAS-II*, vol. 61, no. 4, pp. 259–263, 2014- P. Meinerzhagen,
**A. Teman**, A. Fish and A. Burg,*"***Impact of body biasing on the retention time of gain-cell memories,**"*The Journal Of Engineering*, vol. 1, no. 1, 2013 - P. Meinerzhagen,
**A. Teman**, R. Giterman, A. Burg, and A. Fish, “,” MDPI JLPEA, vol. 3, no. 2, pp. 54–72, 2013*Exploration of sub-VT and near-VT 2T gain-cell memories for ultra-low power applications under technology scaling* - H. Dagan,
**A. Teman**, E. Pikhay, V. Dayan, A. Mordakhay, Y. Roizin, and A. Fish, “,”*A low-power DCVSL-like GIDL-free voltage driver for low-cost RFID nonvolatile memory**IEEE JSSC*, vol. 4, no. 6, pp. 1497–1510, 2013 **A. Teman**, A. Mordakhay, and A. Fish, “,” Microelectronics Journal, vol. 44, no. 3, pp. 236–247, 2013*Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell***A. Teman**, H. Dagan, V. dayan, E. Pikhay, Y. Roizin, and A. Fish,*"***Zero-cost ultra-low power non-volatile memory module for RFID applications**,"*TowerJazz Technical Journal*, vol. 4, pp. 46-49, July 2013- A. Spivak,
**A. Teman**, A. Belenky, O. Yadid-Pecht, and A. Fish, “,” MDPI Sensors, vol. 12, no. 8, pp. 10067–10085, 2012*Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel* **A. Teman**, O. Yadid-Pecht, and A. Fish, “,” IEEE Sensors Journal, vol. 12, no. 4, pp. 773–784, 2012*Leakage reduction in advanced image sensors using an improved AB2C scheme***A. Teman**, A. Mordakhay, J. Mezhibovsky, and A. Fish, “,” IEEE TCAS-II, vol. 59, no. 12, pp. 873–877, 2012*A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability*- A. Spivak,
**A. Teman**, A. Belenky, O. Yadid-Pecht, and A. Fish,*"***Power-performance tradeoffs in wide dynamic range image sensors with multiple reset approach,**"*MDPI J. Low Power Elec. and App*., vol. 1, no. 1, pp. 59-76, 2011 **A. Teman**, L. Pergament, O. Cohen, and A. Fish, ""*A minimum leakage quasi-static RAM bitcell*,*MDPI J. Low Power Elec. and App*., vol.1, no. 1, pp. 204-218, 2011**A. Teman**, L. Pergament, O. Cohen, and A. Fish, “,” IEEE JSSC, vol. 46, no. 11, pp. 2713–2726, 2011*A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM)***A. Teman**, O. Yadid-Pecht, and A. Fish, "**Large VLSI arrays - power and architectural perspectives**" International Journal of Information Technologies and Knowledge (IJ ITK), vol. 4, no. 1, pp. 76-90, 2010

#### Peer-reviewed Conference Proceedings:

- Y. Kra, T. Noy and
**A. Teman**, "Wavepro: Clock-less wave-propagated pipeline compiler for low-power and high-throughput computation" in*Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE)*, DATE 2020 - A. Shalom, A. Fish and
**A. Teman**, "A 9pW/bit 440mV 3T Gain-Cell eDRAM for ULP Applications in 28nm FD-SOI" in*Proc. of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)*, October 2019 - T. Munk, H. Kugler, O. Maori and
**A. Teman**, "TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches,"*2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)*,pp. 1-4, Hsinchu, Taiwan, 2019 - O. Maltabashi, H. Marinberg, R. Giterman and
**A. Teman**, "A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing,"*2018 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-5, Florence, 2018 - A. Bonetti, J. Constantin,
**A. Teman**and A. Burg, "A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI,"*2018 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-4, Florence, 2018 - R. Giterman, A. Fish, A. Burg and
**A. Teman**, "A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI," in*Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018.* - A. Bonetti,
**A. Teman**, P. Flatresse and A. Burg, "Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters," in*Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018* - R. Golman, R. Giterman and
**A. Teman**, "A Dual-Negative Word-Line Technique for Improving Read Access in GC-eDRAM Arrays**,**" in*Proc. of the IEEE Int. Conf. on the Science of Electrical Engineering (ICSEE)*, December 2018 - A. Shalom, R. Giterman and
**A. Teman**, "High Density GC-eDRAM Design in 16nm FinFET,"*2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)*, pp. 585-588, Bordeaux, December 2018 - R. Golman, R. Giterman and
**A. Teman**, "Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism,"*2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)*, pp. 589-592, Bordeaux, December 2018 - R. Giterman,
**A. Teman**and A. Fish, "A 14.3pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI,"*2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)*, pp. 1-2 Burlingame, CA, USA, Oct. 2018 - R. Giterman, R. Golman, A. Shalom, O. Maltabashi, A. Fish and
**A. Teman**, "Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications,"*2018 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1-1, Florence, May 2018 - R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and
**A. Teman**, "An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications,"*ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference*, pp. 308-311, Leuven, Sept. 2017 - R. Giterman, A. Teman and A. Fish, "A 11.5pW/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI,"
*2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)*, pp. 1-3, San Francisco, CA, 2017 - R. Giterman,
**A. Teman**, P. Meinerzhagen,in*“Highly Configurable Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation,”**Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS)*, 2017 - J. Constantin, A. Bonetti,
**A. Teman**, C. Mueller, L. Schmid, and A. Burg, “,”in*DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment**ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference*, pp. 261-264, Lausanne, September 2016 - D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak,
**A. Teman**, et al., “*193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-Eﬃcient Parallel and Sequen*,” in*tial Digital Processing**2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)*, pp. 1-3, Yokohama, April 2016 - R. Giterman,
**A. Teman**, P. Meinerzhagen, A. Burg, and A. Fish, “,” in*A process compensated gain cell embedded DRAM for ultra low power variation aware design**2016 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1006-1009, Montreal, QC, 2016 - R. Ghanaatian, P. Whatmough, J. Constantin,
**A. Teman**, and A. Burg, “,” in*A low-power correlator for wake-up receivers with algorithm pruning through early termination**2016 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 2667-2670, Montreal, QC, May 2016 - R. Giterman,
**A. Teman**, L. Atias, and A. Fish, “,” in*A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications**Proc. of IEEE S3S*, pp. 1-2, October 2015 - S. Ganapathy, G. Karakonstantis,
**A. Teman**, and A. Burg, “,” ins*Mitigating the impact of faults in unreliable memories for error-resilient application**Proc. of the Design Automation Conference (DAC) DAC*, pp. 102:1-106:6, ACM, NY., USA, 2015 - S. Ganapathy,
**A. Teman**, R. Giterman, A. P. Burg, and G. Karakonstantis, “” in*Approximate computing with unreliable dynamic memories,**Proc. of Int. New Circuits And Systems Conference (NEWCAS)*, pp. 1-4, June 2015 Special session on Approximate Computing. - A. Bonetti,
**A. Teman**, and A. P. Burg, “,” in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2015*An overlap-contention free true-single-phase clock dual-edge-triggered ﬂip-ﬂop* **A. Teman**, G. Karakonstantis, R. Giterman, P. Meinerzhagen, and A. Burg, “,” in Proc. of the Design Automation and Test in Europe Conference Exhibition (DATE), DATE 2015, pp. 489–494, San Jose, CA, USA, 2015*Energy versus data integrity trade-oﬀs in embedded high-density logic compatible dynamic memories***A. Teman**, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, “,” in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC) , pp. 81–86, 2015*Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI*- L. Atias,
**A. Teman**and A. Fish, "Single event upset mitigation in low power SRAM design,"*2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI)*, pp. 1-5, Eilat, 2014 - R. Giterman,
**A. Teman**, P. Meinerzhagen, A. Burg and A. Fish, “”in*4T gain-cell with internal-feedback for ultra-low retention power at scaled CMOS nodes,**2014 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 2177-2180, Melbourne VIC, 2014 **A. Teman**, “,” in*Dynamic Stability and Noise Margins of SRAM Arrays in Nanoscaled Technologies**IEEE FTFC 2014*, pp. 1-5, Monte Carlo, Monaco- A. Vaknin, O. Yona and
**A. Teman**, "A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation,"*2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)*, pp. 1-2, Monterey, CA, 2013 - L. Atias,
**A. Teman**and A. Fish, "A 13T radiation hardened SRAM bitcell for low-voltage operation,"*2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)*, pp. 1-2, Monterey, CA, 2013 - N. Edri, S. Fraiman,
**A. Teman**and A. Fish, "Data retention voltage detection for minimizing the standby power of SRAM arrays,"*2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel*, pp. 1-5, Eilat, 2012 **A. Teman**, P. Meinerzhagen, A. Burg and A. Fish, "Review and classification of gain cell eDRAM implementations,"*2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel*, pp. 1-5, Eilat, 2012- P. Meinerzhagen,
**A. Teman**, A. Mordakhay, A. Burg and A. Fish, "A sub-VT 2T gain-cell memory for biomedical applications,"*2012 IEEE Subthreshold Microelectronics Conference (SubVT)*, pp. 1-3, Waltham, MA, 2012 - H. Dagan,
**A. Teman**, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, "A low-cost low-power non-volatile memory for RFID applications,"*2012 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1827-1830, Seoul, 2012 - H. Dagan,
**A. Teman**, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, "A GIDL free tunneling gate driver for a low power non-volatile memory array,"*2012 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 452-455, Seoul, 2012 - J. Mezhibovsky,
**A. Teman**and A. Fish, "State space modeling for sub-threshold SRAM stability analysis,"*2012 IEEE International Symposium on Circuits and Systems (ISCAS)*, pp. 1823-1826, Seoul, 2012 - I. Schwartz,
**A. Teman**, R. Dobkin and A. Fish, "Near-threshold 40nm Supply Feedback C-element,"*2011 3rd Asia Symposium on Quality Electronic Design (ASQED)*, pp. 74-78, Kuala Lumpur, 2011 - J. Mezhibovsky,
**A. Teman**and A. Fish, "Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM,"*2011 IEEE International SOC Conference*, pp. 136-141, Taipei, 2011 **A. Teman**and A. Fish, "Sub-threshold and near-threshold SRAM design,"*2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel*, pp. 000608-000612, Eilat, 2010**A. Teman**, O. Yadid-Pecht and A. Fish, "An Improved AB2C scheme for leakage power reduction in image sensors with on-chip memory,"*SENSORS, 2009 IEEE*, pp. 193-196, Christchurch, 2009- S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, "Ultra-low power subthreshold flip-flop design,"
*2009 IEEE International Symposium on Circuits and Systems*, pp. 1573-1576, Taipei, 2009 - S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, "Digital subthreshold logic design - motivation and challenges,"
*2008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel*, pp. 702-706 , Eilat, 2008 - A. Teman, S. Fisher, L. Sudakov, A. Fish and O. Yadid-Pecht, "Autonomous CMOS image sensor for real time target detection and tracking,"
*2008 IEEE International Symposium on Circuits and Systems*, pp. 2138-2141, Seattle, WA, 2008

**Select Talks**

- O. Maltabashi and
**A. Teman**, "", in CDNLive Israel, October 2017**Controlled Placement of Standard Cell Memories with Innovus Implementation System** **A. Teman**, "", in CDNLive Israel, October 2016**FD-SOI Standard Cell Characterization with Cadence Liberate**- A. Bonetti, N. Preyss, A. Burg, and
**A. Teman**, “,” in CDNLive Israel, October 2015*Dual-edge triggered clocking - how we can use it and when* - A. Bonetti, N. Preyss,
**A. Teman**and A. Burg, “**Automated Integration of Dual-Edge Triggered Clocking Into the Standard Design Flow**,” in CDNLive EDMA, April 2015 - A. Bonetti, J. Constantin,
**A. Teman**and A. Burg, “,” in Nanotera Annual Meeting 2015, May 2015*Circuits and techniques for dynamic timing monitoring in microprocessors* **A. Teman**, G. Karakonstatis, S. Ganapathy, and A. Burg, “,” in Workshop on Approximate Computing (WAPCO), January 2015*Exploiting application error resilience for energy savings in memories***A. Teman**and A. Fish, “,” in CDNLive Israel, September 2012*SRAM stability in the nanoscale era***A. Teman**and A. Fish, “,” in ChipEx 2011, May 2011*Low voltage logic and SRAM design*