Hebrew Name: מעגלי ומערכות וי.אל.אס.איי. דיגיטליים
BIU Course Number: 83-612
Complete Playlist on YouTube: English, עברית
Preparation of these recorded
lectures was kindly supported by Intel.
- All of my Kahoots can be found under my profile on Kahoot.com
- Introduction
- Verilog (Synthesizeable RTL)
- Logic Synthesis - Part I (Standard Cell Libraries)
- Logic Synthesis - Part II (Elaboration and Technology Mapping)
- English (Accompanying Slides)
- עברית (Use English Version Slides): Section 4a, 4b, 4c, 4d, 4e, 4f
- Static Timing Analysis (STA)
- Moving to the Physical Domain (incl. Floorplan)
- Standard Cell Placement
- Clock Tree Synthesis
- English (Slides)
- Section 8a: Clock Tree Synthesis (CTS)
- Section 8b: Clock Distribution
- Section 8c: Clock Concurrent Optimization (CCOpt)
- Section 8d: Clock Tree Synthesis in EDA Tools
- Section 8e: Clock Routing and Clock Tree Analysis
- Section 8f: Clock Generation
- Section 8g: Clock Domain Crossing (CDC)
- Kahoot! for discussing Lecture 8
- עברית (Slides): Section 8a, 8b-c, 8d, 8e (Sections 8f and 8g only in English)
- English (Slides)
- Gobal and Detailed Routing
- Input/Output Circuits and Packaging
- Chip Finishing and Sign-Off
Additional Material:
Digital-on-top Physical Verification (Fullchip LVS/DRC)
Power Intent and Low Power Methodology
Design For Test
Other Tutorials:
-
- Introduction to Tcl: The Tool Command Language: Part 1, Part 2
- TCLPY - Interfacing Python with your EDA Tools - Udi Kra
- Abstract Generation (LEF/LIB) for Custom Blocks - Odem Harel