Digital VLSI Design

Hebrew Name: מעגלי ומערכות וי.אל.אס.איי. דיגיטליים

BIU Course Number: 83-612

Lecture Slides and Video Recordings

Complete Playlist on YouTube: English, עברית

  1. Introduction
  2. Verilog (Synthesizeable RTL)
  3. Logic Synthesis - Part I (Standard Cell Libraries)
  4. Logic Synthesis - Part II (Elaboration and Technology Mapping)
  5. Static Timing Analysis (STA)
  6. Moving to the Physical Domain (incl. Floorplan)
  7. Standard Cell Placement
  8. Clock Tree Synthesis
  9. Gobal and Detailed Routing
  10. Input/Output Circuits and Packaging
  11. Chip Finishing and Sign-Off