Hebrew Name: מעגלי ומערכות וי.אל.אס.איי. דיגיטליים
BIU Course Number: 83-612
Lecture Slides and Video Recordings
Complete Playlist on YouTube: English, עברית
- All of my Kahoots can be found under my profile on Kahoot.com
- Introduction
- Verilog (Synthesizeable RTL)
- Recording - English (Accompanying Slides)
- Supplementary Material: Writing Synthesizeable RTL (Slides)
- Kahoot! for discussing Lecture 2
- Recording - עברית (Accompanying Slides)
- Recording - English (Accompanying Slides)
- Logic Synthesis - Part I (Standard Cell Libraries)
- Logic Synthesis - Part II (Elaboration and Technology Mapping)
- Static Timing Analysis (STA)
- Moving to the Physical Domain (incl. Floorplan)
- Standard Cell Placement
- Clock Tree Synthesis
- Gobal and Detailed Routing
- Input/Output Circuits and Packaging
- Chip Finishing and Sign-Off