Research Tapeouts

2019 - SoC2
System-on-Chip

  • Technology: TSMC 16FFC
  • Co-academic director and leader of GC-eDRAM block

2018 - Kwak
Gain Cell eDRAM Test Chip and more

  • Technology: Samsung 28nm FD-SOI
  • Project Manager

2017 - Martini
Gain Cell eDRAM Test Chip and more

  • Technology: ST 28nm FD-SOI
  • Project Manager

2016 - BEER
Gain Cell eDRAM Test Chip and more

  • Technology: ST 28nm FD-SOI
  • Project Manager

2016 - DAFNA
Gain Cell eDRAM Test Chip

  • Technology: TSMC 28nm
  • First GC-eDRAM test chip in a 28nm bulk technology, designed in collaboration with Mellanox.
  • Project Manager

2016 - Polar Bear
Polar Decoder chip

  • Technology: ST 28nm FD-SOI
  • Advisor for complex physical implementation

2015 - PULP-III
Flexible multi-core platform for energy efficient computing

  • Technology: ST 28nm FD-SOI
  • Participant in large, multi-partner project with ST-Microelectronics, UNIBO, ETH-Zurich, and CEA-Leti.
  • Participant in architecture design and planning of body-bias generation block.

2015 - dynOR
Scalable CPU with early-edge detection and clock generation unit

  • Technology: ST 28nm FD-SOI
  • Project leader and head engineer.

2014 - CAMEL
Memory and cryptography test chip

  • Techonology: TSMC 65nm LP
  • Advisor for design and physical implementation of multi-project test chip with Bar-Ilan University.

2014 - DDFSE
60GHz wi-fi test chip

  • Technology: TSMC 40nm LP
  • Advisor for physical implementation of 2 Million gate, very complex hard macro.

2014 - PULP-II
Flexible multi-core platform for energy efficient computing

  • Technology: ST 28nm FD-SOI
  • Participant in large, multi-partner project with ST-Microelectronics, UNIBO, and ETH-Zurich.
  • In charge of Standard Cell Memory block design and integration and special cell characterization and integration.

2013 - GREENBELT2
Gain-cell embedded DRAM and SRAM for space applications test chip

  • Technology: UMC 0.18µm
  • Led project, designed all included components, and carried out tape-out procedure, in collaboration with EPFL.

2012 - GREENBELT
Gain-cell embedded DRAM test chip2010–2012

  • Technology: UMC 0.18µm
  • Led project, designed all included components, and carried out tape-out procedure, in collaboration with EPFL.

2010–2012 - RFID
Single Chip RFID Demonstrator in standard CMOS process

  • Technology: TowerJazz 0.18µm
  • Participated in the design, tape-out procedures and measurements of 10 test-chips, as part of a multi-year project.
  • Project culminated with a fully operational low-cost low-power RFID Demonstrator.
  • Cooperation with Tel Aviv University and Tower Semiconductor.

2010 - RAMBO
Subthreshold SRAM test chip.

  • Technology: TSMC 40nm LP
  • Led project, designed all included components, carried out tape-out procedure and measurements.
  • First 40 nm test chip by an academic group in Israel.
  • Cooperation with Zoran in tape-out procedure.

2008 - Sub-Vt
Subthreshold logic test chip including AB2C smart imager

  • Technology: TSMC 80nm
  • Responsible for several of the included test circuits and components.
  • Led full-chip integration and tape-out. Participated in measurements.
  • Cooperation with Zoran in tape-out procedure.