Patents

  • I. Levi, O. Keren and A. Fish, "Pseudo-Asynchronous digital circuit design",  U.S. Patent No: 11,023,632 , granted June 2021.
  • M. Avital, I. Levi, A. Fish, O. Keren, "Randomized logic against side channel attacks", US patent No.: 10,951,39, granted, Mar. 16, 2021
  • I. Levi, O. Keren, and A. Fish. "Pseudo-asynchronous digital circuit design". U.S. Patent 10,572,619, granted Feb. 25, 2020.
  • I. Levi, O. Keren and A. Fish, "Data-dependent delay circuits", US Patent:  10,521,530 granted December 2019.
  • H. Rabii, Y. Neumeier, Y. Bodner, T. Sdika and O. Keren, "Separable robust coding", US 2019-0259466, Aug 2019.
  • A. Fish, O. Keren, Y. Weizman and M. Elkoni, “Information Redistribution to reduce side channel leakage”, PCT application No.: PCT/IL2019/050230, February 2019.
  • M. Avital, A. Fish, H. Dagan, O. Keren, "Multi-topology logic gates", US patent No: 10,169,617, granted January 2019.
  • R. Giterman, I. Levi, O. Keren, and A. Fish, “Secured memory”, PCT application No: PCT/IL2018/051338, US 16/769,664, December 2018.
  • A. Fish, M. Avital, A. Mordakhay, Y. Weizman and O. Keren, “Compact Bit Generator”, Application No.: US 16/224,869, December 2018.
  • E. Ofek and O. Keren, "Scalar product and parity check", United States Patent 6760880 , filing date 08.1999 publication date 06.2004.