Journal Papers

  1. Halman N. and Wimer S., "Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions,” Information Processing Letters, Vol. 170, Apr. 2021, DOI: 10.1016/j.ipl.2021106114.
  2. Frankel B., Sarfati E., Wimer S. and Birk Y. , "Post-silicon analysis of shielded interconnect delays for useful skew clock design,” IEEE Trans. on Electron Devices, Vol. 66, No. 11, Nov. 2019, pp. 4875-4882, DOI: 10.1109/TED.2019.2938621.
  3. Wimer U. and Wimer S., “Resource allocation in rooted trees for VLSI applications,” Optimization, Feb. 2019, DOI: 10.1080/02331934.2019.1576669.
  4. Herman R., Frankel B. and Wimer S., "Optimal queuing-based memory refreshing algorithm for energy efficient processors,” Computers and Electrical Engineering, Vol. 71, Oct 2018, pp. 505-514, DOI: 10.1016/j.compeleceng.2018.07.057.
  5. Sarfati E., Frankel B., Birk Y. and Wimer S., "Accurate shielded interconnect delay estimation by reconfigurable ring oscillator,” IEEE Trans. on Circuits and Systems I, Vol. 65, No. 10, Oct 2018, pp. 3435-3444, DOI: 10.1109/TCSI.2018.2825999.
  6. Frankel B., Herman R. and Wimer S., "Queuing-based eDRAM refreshing for ultra-low power processors,” IEEE Trans. on Computers, Vol. 67, No. 9, Sept 2018, pp. 1331-1340, DOI: 10.1109/TC.2018.2811470.
  7. Sarfati E., Frankel B., Birk Y. and Wimer S., "Optimal VLSI delay tuning by space tapering with clock-tree application,” IEEE Trans. on Circuits and Systems I, Vol. 64, No. 8, Aug 2017, pp. 2160-2170, DOI: 10.1109/TCSI.2017.2695100.
  8. Gluzer D. and Wimer S., “Probability-driven multibit flip-flop integration with clock gating,” IEEE Trans. on VLSI Systems, Vol. 25, No. 3, March 2017, pp. 1173-1177, DOI: 10.1109/TVLSI.2016.2614004.
  9. Kazimirsky A. and Wimer S., “Opportunistic refreshing algorithm for eDRAM memories,” IEEE Trans. on Circuits and Systems I, Vol. 63, No. 11, Nov 2016, pp. 1921-1932, DOI: 10.1109/TCSI.2016.2600538.
  10. Albeck A. and Wimer S., “Energy efficient computing by multi-mode addition,” Integration – the VLSI Journal, Vol. 55, 2016, pp. 176-182, DOI: 10.1016/j.vlsi.2016.06.002.
  11. Frankel B. and Wimer S., “Optimal VLSI delay tuning by wire shielding,” Journal of Optimization Theory and Applications, Vol. 170, No. 3, 2016, pp. 1060-1067, DOI: 10.1007/s10957-016-0960-8.
  12. Wimer S., “Optimal weight allocation in rooted trees,” Journal of Combinatorial Optimization, Vol. 31, No. 3, 2016, pp. 1023-1033, DOI 10.1007/s10878-014-9807-0.
  13. Kaplan Y. and Wimer S., “Mixing drivers in clock-tree for power supply noise reduction,” IEEE Trans. on Circuits and Systems I, Vol. 62, No. 5, May 2015, pp. 1382-1391, DOI: 10.1109/TCSI.2015.2411778.
  14. Wimer S., “Easy and difficult exact covering problems arising in VLSI power reduction by clock gating,” Discrete Optimization, Vol. 14, 2014, pp. 104-110, DOI 10.1016/j.disopt.2014.08.004.
  15. Levi I., Albeck A., Fish A. and Wimer S., “A low energy and high performance DM2 adder,” IEEE Trans. on Circuits and Systems I, Vol. 61, No. 11, Nov 2014, pp. 3175-3183, DOI 10.1109/TCSI.2014.2334793.
  16. Wimer S. and Stanisavsky A., “Energy efficient hybrid adder architecture,” Integration – the VLSI Journal, Vol. 48, 2015, pp. 109-115, DOI 10.1016/j.vlsi.2014.06.002.
  17. Wimer S., Gluzer D. and Wimer U., “Using well-solvable minimum cost exact covering for VLSI clock energy minimization,” Operations Research Letters, Vol. 42, 2014, pp. 332-336, DOI 10.1016/j.orl.2014.05.010.
  18. Wimer S., Albeck A. and Koren I., “A low energy dual-mode adder,” Computers and Electrical Engineering, Vol. 40, No. 5, July 2014, pp. 1524-1537, DOI 10.1016/j.compeleceng.2014.04.012.
  19. Moiseev K., Wimer S. and Kolodny A., “Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing,” Integration – the VLSI Journal, Vol. 48, 2015, pp. 116-128, DOI 10.1016/j.vlsi.2014.03.002.
  20. Shaphir E., Pinter R. Y. and Wimer S., “Efficient cell-based migration of VLSI layout ,” Optimization and Engineering, Vol. 16, 2015, pp. 203-223, DOI 10.1007/s11081-014-9257-7.
  21. Shaphir E., Pinter R. Y. and Wimer S., “Cell-based interconnect migration by hierarchical optimization,” Integration – the VLSI Journal, Vol. 47, 2014, pp. 161-174, DOI 10.1016/j.vlsi.2013.10.003.
  22. Wimer S. and Albahari A., “A look-ahead clock gating based on auto-gated flip-flops,” IEEE Trans. on Circuits and Systems I, Vol. 61, No. 5, May 2014, pp. 1465-1472, DOI 10.1109/TCSI.2013.2289404.
  23. Wimer S., “On optimal flip-flop grouping for VLSI power minimization,” Operations Research Letters, Vol. 41, 2013, pp. 486-489, DOI 10.1016/j.orl.2013.06.002.
  24. Wimer S. and Koren I., “Design flow for flip-flop grouping in data-driven clock gating,” IEEE Trans. on VLSI Systems, Vol. 22, No. 4, Apr 2014, pp. 771-778, DOI 10.1109/TVLSI.2013.2253338.
  25. Wimer S., “Planar CMOS to multi-gate layout conversion for maximal fin utilization,” Integration – the VLSI Journal, Vol. 47, 2014, pp. 115-122, DOI 10.1016/j.vlsi.2013.03.004.
  26. Wimer S. and Koren I., “The optimal fan-out of clock network for power minimization by adaptive gating,” IEEE Trans. on VLSI Systems, Vol. 20, No. 10, Oct 2012, pp. 1772-1780, DOI 10.1109/TVLSI.2011.2162861.
  27. Moiseev K., Kolodny A. and Wimer S., “The complexity of VLSI power-delay optimization by interconnect resizing,” Journal of Combinatorial Optimization, Vol. 23, No. 2, 2012, pp. 292-300, DOI 10.1007/s10878-010-9355-1.
  28. Emanuel B., Wimer S. and Wolansky G., “Using well-solvable quadratic assignment problems for VLSI interconnect applications,” Discrete Applied Mathematics, Vol. 160, No. 4-5, 2012, pp. 525-535, DOI 10.1016/j.dam.2011.11.017.
  29. E. Cela, N. S. Schmuck, S. Wimer and G. J. Woeginger, “The Wiener maximum quadratic assignment problem,” Discrete Optimization, No. 8, 2011, pp. 411-416.
  30. Wimer S., Moiseev K. and Kolodny A., “On VLSI interconnect optimization and linear ordering problem,” Optimization and Engineering, No. 12, 2011, pp. 603-609.
  31. Moiseev K., Kolodny A. and Wimer S., “Interconnect bundle sizing under discrete dsign rules”, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 29, No. 10, Oct. 2010, pp. 1650 – 1654.
  32. Moiseev, K., Kolodny A. and Wimer S., “Power-delay optimization in VLSI microprocessors by wire spacing,” ACM Trans. on Design Automation of Electronic Systems, Vol. 14, No. 4, Aug 2009, Article No. 55.
  33. Moiseev K., Kolodny K. and Wimer S., “Timing-aware power-optimal ordering of signals,” ACM Trans. on Design Automation of Electronic Systems, Vol. 13, No. 4, Sept 2008, Article No. 65.
  34. Moiseev K., Wimer S. and Kolodny A., “On optimal ordering of signals in parallel wire bundles,” Integration – the VLSI Journal, Vol. 41, 2008, pp. 253 – 268.
  35. Wimer S., Michaely S., Moiseev K. and Kolodny A., “Optimal bus sizing in migration of processor design,” IEEE Trans. on Circuits and Systems - I, 2006, pp. 1089 – 1100.
  36. Feldman J. A., Wagner I. A. and Wimer S., “An efficient algorithm for some multirow layout problems,” IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, pp. 1178 – 1185.
  37. Wimer S., Cederbaum I and Koren I., “On paths with the shortest average arc length in weighted graphs,” Discrete Applied Mathematics, 1993, pp. 169 – 179.
  38. Cederbaum I., Koren I. And Wimer S., “Balanced block spacing for VLSI layout,” Discrete Applied Mathematics, 1992, pp. 303 – 318.
  39. Bar-Yehuda R., Feldman J. A., Pinter R. Y. and Wimer S., “Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation,” IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, pp. 737 – 743.
  40. Wimer S., Koren I. And Cederbaum I., “Optimal aspect ratios of building blocks in VLSI,” IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, pp. 139 – 145.
  41. Wimer S., Koren I. and Cederbaum I., “Floorplans, planar graphs and layouts,” IEEE Trans. on Circuits and Systems, 1988, pp. 267 – 278.
  42. Wimer S. and Koren I., “Analysis of strategies for constructive general block placement,” IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, pp. 371 – 377.
  43. Wimer S., Pinter R. Y. and Feldman J. A., “Optimal chaining of CMOS transistors in functional cell,” IEEE Tran. on CAD of Integrated Circuits and Systems, 1987, pp. 795 – 801.