Conference Papers

1. Wimer S. and Koren I., “Energy efficient deeply fused dot-product multiplication architecture,” 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 115-122, July 2016.
2. Wimer S., Stanislavsky A. and Kolodny A., “Energy efficient addition by two-sided carry-reverse computation,” IEEE 27th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2012.
3. Kaplan Y. and Wimer S., “Post optimization of a clock tree for power supply noise reduction,” IEEE 27th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2012.
4. Ran Manevich, Israel Cidon, Avinoam Kolodny, Isaskhar Walter and Shmuel Wimer, “A cost effective centralized adaptive routing for networks-on-chip,” 14th EUROMICRO Conference on Digital System Design, Aug 2011, pp. 39-46.
5. Cohen I., Koren I. and Wimer S., “Adaptive clock gating for shift register based circuits,” IEEE 26th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2010.
6. Moiseev K., Kolodny A., and Wimer S., “Interconnect power and delay optimization by dynamic programming in gridded design rules,” International Symposium on Physical Design – ISPD, March 2010.
7. Moiseev K., Wimer S. and Kolodny A., “Power saving in CMOS processors by optimal wire spacing,” IFIP/IEEE Intl. Conf. on VLSI - VLSI SoC 2008.
8. K. Moiseev, S. Wimer and A. Kolodny, "Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing", Proceedings of International Symposium on Circuits and Systems, pp. 329-332, May 2006.
9. Michaely S., Wimer S. and Kolodny A., “Optimal resizing of bus wires in layout migration,” ICECS2004 - IEEE 11th International Conference on Electronics, Circuits, and Systems, 2004, pp 411-414.
10. Cohen U., Grishchenko L., Nitzan R., Topaz M. and Wimer S., “AMPS and SiClone integration for design migration of Banias microprocessor,” DTTC, Intel Design Technology and Testing Conference, July 2002.
11. Nitzan R. and Wimer S., “AMPS and SiClone integration for implementing 0.18u to 0.13u design migration”, SNUG – Synopsys Users Group, San Jose, March 2002.
12. Feldman J. A., Wagner I. A. and Wimer S., “An efficient algorithm for some multirow layout problems,” Proceedings of the MCNC Workshop on VLSI Layout, 1992.
13. Solel E. and Wimer S., “Breathing maze router for analog VLSI cell generation,” Proceedings of the International Conference on CAD/CAM and AMT, 1989.
14. Bar-Yehuda R., Feldman J. A., Medan Y., Turgeman A. and Wimer S., “Integrated image design and complex standard CMOS cell generator,” IEEE 16th Conference of Electrical and Electronics Engineers in Israel, 1988.
15. Wimer S., Cederbaum I. and Koren I., “Optimal aspect ratios of building blocks in VLSI,” Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, pp. 66 – 72.
16. Bar-Yehuda R., Feldman J. A., Pinter R. Y. and Wimer S., “Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation,” Proceedings of the 5th MIT VLSI Conference, 1989, pp. 66 – 72.
17. Wimer S., Cederbaum I. and Koren I., “Optimal aspect ratios of building blocks in VLSI,” Abstracts of 22nd General Assembly of URSI, 1987.
18. Feldman J. A., Pinter R. Y. and Wimer S., “An optimal cell generation and composition system,” IEEE 15th Conference of Electrical and Electronics Engineers in Israel, 1987.
19. Wimer S. and Koren I., “Constructive placement of general blocks in VLSI under uncertainties in the position of ports,” ICCAD86 – IEEE International Conference on CAD, 1986, pp. 458 – 461.
20. Wimer S., Pinter R. Y. and Feldman J. A., “Optimal chaining of CMOS transistors in functional cell,” ICCAD86 – IEEE International Conference on CAD, 1986, pp. 66 – 69.
21. Wimer S. and Sharfman N., “HOPLA – PLA optimization and synthesis,” in Proceedings of the 20th ACM/IEEE Design Automation Conference, 1983, pp. 790 – 794.