Tapeouts at Bar Ilan:

Since arriving at Bar Ilan, Prof. Shor has trained students and developed infrastructure to enable Silicon Tapeouts which include analog and digital circuits.  Typically, the training a student requires from the time he/she enters analog till a successful tapeout takes 3 years.  Below is a list of the tapeouts which have been and are being implemented.

• Pathfinder (May, 2017 – 65nm TSMC) – This was the first BIU analog tapeout.  It      included thermal sensors, as well as PUF circuits.  The circuits exhibited excellent functionality and have generated publications in JSSC, TCAS1, TCAS2, SSCL, and ESSCIRC. 

• Pathfinder2 (May 2018 – 65nm TSMC) – This follow-up tapeout included several new PUF circuits, all of which functioned well in Silicon. Papers were published in TCAS1, OJCAS, IEEE Access, CICC 2019, and ISCAS 2019.

• Genesis (May 2019 – 65nm TSMC) – This tapeout included PUFs, a Process Monitor and an ultra-low power bandgap reference. The circuits are fully functional, and papers are being written.

• SOC2 (June 2019 – 16nm TSMC) – Shor’s group participated in this tapeout of the Hiper Consortium and the contribution include an ultra-small, ultra-fast thermal sensor for thermal monitoring of the SOC. Initial debug indicates that the sensor is functional.  Full characterization is in progress.

• Genesis2 (Aug 2019 – 65nm TSMC) – Circuits included a Ring-Oscillator based sensor, a mobility monitor and a Low Voltage Power-On-Reset Circuit. All circuits are functioning well and papers are being prepared.  So far, a papers were accepted or published in ESSCIRC, SSCL, TCAS2 and IEEE Access.

• Snir (Feb 2020, 65nm TSMC) – This chip contains an LDO, a Process Monitor, a Noise modeling circuit, two different Droop detector circuits, a Dual Mode Logic block, and a Switch-capacitor DC-DC converter.  Papers have been accepted in JSSC and ESSCIRC.