Publications

Journals

 

  1. R. Breuer and I. Levi, "How Bad Are Bad Templates Optimistic Design Stage Side-Channel Security Evaluation and its Cost", Cryptography 4.4 (2020): 36
  2. G. Cassiers, B. Grégoire, I. Levi, and F.X. Standaert, "Hardware Private Circuits: From Trivial Composition to Full Verification," IEEE Transactions on Computers, doi: 10.1109/TC.2020.3022979
  3. I. Levi, D. Bellizia, D. Bol, and F-X. Standaert, "Ask Less Get More: Side-Channel Signal Hiding, Revisited", IEEE Transactions of Circuits And Systems-I (TCAS-I): regular papers, DOI: 10.1109/TCSI.2020.3005338.
  4. B. Bilgin, L. De Meyer, S. Duval, I. Levi,  and F.X. Standaert, "Low AND Depth and Efficient Inverses: a Guide on S-boxes for Low-latency Masking". IACR Transactions on Symmetric Cryptology, pp. 144-184, 2020
  5. I. Levi, D. Bellizia, and F. X. Standaert. "Beyond Algorithmic Noise. Or How to Shuffle Parallel Implementations?", International Journal of Circuit Theory and Applications, vol. 48, issue 5, pp. 674-695, May 2020
  6. G. Cassiers, B. Grégoire, I. Levi, and F.X. Standaert, "Hardware Private Circuits: From Trivial Composition to Full Verification". cryptology eprint, 2020
  7. J. Knechtel, E.B. Kavun, F. Regazzoni, A. Heuser, A. Chattopadhyay, D. Mukhopadhyay,  S. Dey, Y. Fei, Y. Belenky, I. Levi and T. Güneysu, "Towards secure composition of integrated circuits and electronic systems: On the role of EDA" . arXiv preprint arXiv:2001.09672, 2020.
  8. K. Nawaz , L. Van Brandt, I. Levi, F. X. Standaert and D. Flandre, "A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs" in Integration, the VLSI Journal, vol. 68, pp. 71-79, September 2019
  9. D. Bellizia, F. Berti, O. Bronchain, G. Cassiers, S. Duval, C. Guo, G. Leander, G. Leurent, I. Levi, C. Momin and O. Pereira, "Spook: Sponge-Based Leakage-Resilient Authenticated Encryption with a Masked Tweakable Block Cipher". Submission to NIST Lightweight Cryptography, 2019
  10. I. Levi, D. Bellizia and F. X. Standaert, "Reducing a Masked Implementation’s Effective Security Order with Setup Manipulations and an Explanation Based on Externally-Amplified Couplings" in IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 293-317, no. 2, Feb. 2019
  11. R. Taco, I. Levi, M. Lanuzza and A. Fish, "An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 $\times$ 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI," in IEEE Journal of Solid-State Circuits, pp. 560-568, vol. 54, no. 2,  Feb. 2019
  12. I. Levi, A. Fish, and O. Keren. "Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 1 (2018): 82-95.
  13. R. Giterman, M. Vicentowski, I. Levi, Y. Weizman, O. Keren, and A. Fish. "Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 99 (2018): 1-5.
  14. K. Nawaz, I. Levi, F. X. Standaert, D. Flandre, "A Transient Noise Analysis of Secured Dual-rail based Logic Style" in Feedback, vol. 1, 2018
  15. I. Levi, N. Miller, E. Avni, O. Keren, and A. Fish. "A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits." IEEE Access 5 (2017): 24797-24809.
  16. I. Levi and A. Fish, "Alternative Logic Families for Energy-Efficient and High Performance Chip Design" in Green Photonics and Electronics, pp. 139-172, 2017
  17. I. Levi, A. Fish, and O. Keren. "CPA secured data-dependent delay-assignment methodology." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 2 pp. 608-620, 2017
  18. L. Moyal, I. Levi, A. Teman and A. Fish, "Synthesis of Dual Mode Logic." Integration, the VLSI Journal 55, pp. 246-253, 2016
  19. R. Taco, I. Levi, A. Fish, and M. Lanuzza, "Low Voltage Logic Circuits Exploiting Gate Level Dynamic Body Biasing in 28 nm UTBB FD-SOI ", Solid State Electronics Journal, Elsevier, vol. 117, pp. 185-192, Mar 2016.
  20. M. Avital, I. Levi, O. Keren, and A. Fish. "CMOS based gates for blurring power information." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 7, pp. 1033-1042, 2016
  21. V. Youzhaninov, I. Levi and A Fish "Design Flow and Characterization Methodology for Dual Mode Logic”, IEEE Access, vol. 3, pp. 3089-3101, Jan 2016
  22.  I. Levi, O. Keren, and A. Fish, "Data-Dependent Delays as a Barrier Against Power Attacks" IEEE Transactions on circuits and systems – I: Regular Papers, vol.62, no.8, pp. 2069-2078, Aug. 2015
  23. M. Avital, H. Dagan, I. Levi, O. Keren and A. Fish, “DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes”, IEEE Transactions on circuits and systems – I, vol. 62, issue 1, pp. 149-156, Jan 2015
  24. I. Levi, A. Albeck, A. Fish, and S. Wimer, “A Low Energy and High Performance DM^2 Adder,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 11, pp. 3175–3183, Nov. 2014
  25. I. Levi, A. Belenky and A. Fish, “Logical Effort for CMOS based Dual Mode Logic (DML) gates”, IEEE Transactions on VLSI systems, vol. 22, issue 5, pp. 1042–1053, May 2014.
  26. I. Levi and A. Fish, “Dual Mode Logic: Design for Energy Efficiency and High Performance,” IEEE Access, vol. 1, pp. 258–265, 2013
  27. I. Levi, A. Kaizerman, and A. Fish, “Low voltage dual mode logic: Model analysis and parameter extraction,” Microelectronics Journal, Elsevier, vol. 44, issue 6, pp. 553-560, June 2013
  28. I. Levi, "Design and Implementation of Energy Efficient Dual Mode Logic", 2013

Conference Proceedings:

  1. D. Zooker, M. Elkoni, O. Ohev Shalom, Y. Weizman, I. Levi, O. Keren and A. Fish , "Temporal Power Redistribution as a Countermeasure Against Side-Channel Attacks" 2020 IEEE International Symposium on Circuits and Systems (ISCAS),  Seville, Spain, 2020
  2. Y. Rudin, I. Levi, A. Fish and O. Keren, "FPGA Implementation of pAsynch Design Paradigm," 2019 10th IFIP International Conference on New Technologies, Mobility and Security (NTMS), pp. 1-5, Canary Islands, Spain, 2019
  3. K. Nawaz, I. Levi, F. X. Standaert, and D. Flandre. "A Transient Noise Analysis of Secured Dual-rail based Logic Style" submitted to New Generation of Circuits and Systems (NGCAS) 2018
  4. R. Taco, I. Levi, M. Lanuzza and A. Fish, "Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI," in 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S),pp. 1-3,  Burlingame, CA, 2017
  5. D. Z. Raviv, I. Levi, A. Fish, and O Keren. "Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications." In SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE, pp. 1-2
  6. M. Haber, I. Levi, Y. Yehoshua, and A. Fish. "Differential input output CMOS (DINO-CMOS)—High performance and energy efficient logic family" in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017 IEEE, pp. 1-3
  7. R. Taco, I. Levi, M. Lanuzza, and A. Fish. "Evaluation of Dual Mode Logic in 28nm FD-SOI technology" in Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, pp. 1-4
  8. R. Taco, I. Levi, A. Fish, and M. Lanuzza, "Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology", IEEE International Symposium on Circuits and Systems (ISCAS),  Montreal, 2016
  9. R. Taco, I. Levi, M. Lanuzza, and A. Fish. "Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI" in SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE, pp. 1-2
  10. R. Taco, I. Levi, A. Fish, and M. Lanuzza, "Back-Biasing in 28nm UTBB FD-SOI sLow voltage Ripple Carry Adder with low-Granularity Dynamic Forward”, IEEE SOI-3D-Subthreshold (S3S), 2015
  11. B. Frankel, M. Haber, M. Avital, I. Levi, O. Keren and A. Fish, “Practical design-knobs while performing Power Analysis” Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (Trudevice 2015- COST), Grenoble, France, 13 Mar 2015
  12. R. Taco, I. Levi, A. Fish, and M. Lanuzza, “Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design,” Proc. IEEEI 2014, pp. 1–4, Israel, Dec. 2014
  13. R. Buzilo, B. Likhterov, R. Giterman, I. Levi, A. Fish and A. Belenky, "Approach to integrated energy harvesting voltage source based on novel active TEG array system," 2014 IEEE Faible Tension Faible Consommation, pp. 1-4, Monaco, 2014
  14. I. Levi, O. Bass, A. Kaizerman, A. Belenky and A. Fish, “High Speed Dual Mode Logic Carry Look Ahead Adder”, Proc. IEEE International Symposium on Circuits and Systems, pp. 3037-3040, Seoul, Korea, May 2012

Books and Book Chapters:

  • I. Levi and A. Fish - Dual-Mode-Logic: A New Paradigm for Digital IC Design, Springer (signed), Jan, 2021
  • I. Levi and A. Fish - Alternative Logic Families for Energy-Efficient and Fast chip Design, in Eisenstein, G. and Bimberg, D. eds., "Green Photonics and Electronics", Springer International Publishing, 2017

Invited Talks:

  1. I. Levi, O. Keren and A.Fish “Embedded Randomness and Data Dependancies Design Paradigm: Advantages And Challanges”, Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2018.
  2. I. Levi, O. Keren and A.Fish “Security Aware Pseudo-Asynchronous Circuit Design Style” to be presented, 2nd International Verification and Security Workshop (IVSW), Greece, July 2017.
  3.  I. Levi, O. Keren, and A. Fish, "CPA Secured Data-Dependent Delay-Assignment Methodology", to be presented, IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore MD, USA, 2017.
  4.  M. Avital, I. Levi, O. Keren, and A. Fish, "CMOS Based Gates for Blurring Power Information", to be presented, IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore MD, USA, 2017.
  5.  I. Levi, O. Keren, and A. Fish, "Hardware Security- New Concepts in Side-Channel-Analysis Immunity", CHIPEX2017, May 2017, Israel.
  6.  I. Levi, O. Keren, and A. Fish, "Data-Dependent Delays as a Barrier Against Power Attacks", IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, 2016.
  7. M. Avital, I. Levi, O. Keren, and A. Fish, "DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes", in 2016, IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, 2016.
  8. I. Levi, and A. Fish, "Dual-Mode-Logic", CHIPEX2012, May 2012, Israel.
  9. R. Taco, I. Levi, A. Fish, and M. Lanuzza, "Live Demo: an 88fJ / 40 MHz [0.4V] – 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8x8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI", has been accepted for a live demonstration at the 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Japan May.