Granted

  1. A. Fish, O. Keren, Y. Weizman and M. Elkoni, “Information Redistribution to reduce side channel leakage”, US Patent No. 11,321,460, granted May 2022.
  2. A. Teman, A. Fish, R. Giterman and A. Shalom, "Embedded Dynamic Memory in FinFET Technology", U.S. Patent No: 11,127,455, granted, Sep.21, 2021.
  3. I. Levi, O. Keren and A. Fish, "Pseudo-Asynchronous digital circuit design",  U.S. Patent No: 11,023,632 , granted, June 1, 2021.
  4. R. Giterman, L. Atias, A. Teman and A. Fish, "Complementary Dual-modular Redundancy Memory cell", US patent No: 10,991,421 granted, April 27, 2021.
  5. M. Avital, I. Levi, O. Keren and A. Fish, “Randomized Logic against side channel attacks”, US patent no. 10,951,39 granted, Mar. 16, 2021.
  6. I. Levi, O. Keren, and A. Fish, "Pseudo-asynchronous digital circuit design". U.S. Patent No: 10,572,619, granted Feb. 25, 2020.
  7. I. Levi, O. Keren and A. Fish, "Data-dependent delay circuits", US patent No: US 10,521,530, Granted December 2019.
  8. R. Giterman, A. Teman, E. Mentovich, N. Geuli and A. Fish, “High Density Memory Macro”, US patent No: US 10,497,410, granted December 2019.
  9. M. Avital, H. Dagan, O. Keren and A. Fish, "Multi-Topology Logic Gates", US patent No: 10,169,617, granted January 2019.
  10. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and A. Fish, "Transistor gain cell with feedback", US patent No: 10,002,660, granted June 2018.
  11. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and A. Fish, "Transistor gain cell with feedback", US patent No: 9,691,445, granted June 2017, EP 3138101 Granted Sep. 2019; IL  248633, Granted May 2019
  12. A. Fish, A. Kaizerman, I. Levi and S. Fisher, “Design of Dual mode logic circuits”, US patent No: 9,430,598, granted August 2016.
  13. A. Fish, A. Kaizerman, I. Levy and S. Fisher, "Device and method for dual-mode logic", US patent No: 8,901,965, granted December 2014.
  14. A. Teman, L. Pergament, O. Cohen and A. Fish, “Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation”, US patent No: 8,773,895, granted July 2014.
  15. A. Teman, L. Pergament, O. Cohen and A. Fish, “Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation”, US patent No: 8,531,873, granted September 2013.
  16. O. Yadid-Pecht, Y. Shoshan and A. Fish, ”Digital Watermarking CMOS Sensor”, US patent No: 8,280,098, granted October 2012.
  17. E. Artyomov, A. Fish, B. Maliatski and O. Yadid-Pecht, “Configurable ASIC-based sensing circuit”, EP patent No: 1,946,229, Granted May 2012.
  18. A. Fish and A. Morgenshtein,  “Logic circuit and method of logic circuit design”, US Patent No: 8,188,767, granted May 2012.
  19. A. Morgenshtein, A. Fish and I.A. Wagner, “Logic circuit and method of logic circuit design” US Patent No: 8,161,427, granted April 2012.
  20. A. Fish and A. Morgenshtein, “Logic circuit and method of logic circuit design”, US Patent No: 8,004,316, granted August 2011.
  21. A. Belenky, A. Fish and O. Yadid-Pecht, “Optical Pixel and Image Sensor”, provisional application, US Patent No: 7,990,451, granted August 2011.
  22. A. Morgenshtein, A. Fish and I.A. Wagner, “Logic circuit and method of logic circuit design" US Patent No: 7,716,625, granted May 2010.
  23. A. Morgenshtein, A. Fish, I.A. Wagner, "Logic circuit and method of logic circuit design", US patent  No. 7, 345, 511, granted March 2008.

Applications

  1. R. Giterman, I. Levi, O. Keren, and A. Fish, “Secured memory”, PCT application No: PCT/IL2018/051338, US 16/769,664, December 2018
  2. A. Fish, M. Avital, A. Mordakhay, Y. Weizman and O. Keren, “Compact Bit Generator”, Application No.: US 16/224,869, December 2018
  3. A. Fish, Z. Zalevsky, A. Meiri and O.Bass, "Integrated circuit with photonic elements", PCT application No: PCT/IL2013/050765, March 2014
  4. A. Teman, L. Pergament, O. Cohen  and A. Fish, “Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation”, US application No: US 13103093, November 2012
  5. A. Fish and A. Morgenshtein, “Logic circuit and method of logic circuit design”, US application No: US 13439949, August 2012
  6. A. Morgenshtein, A. Fish and I.A. Wagner, "Logic circuit and method of logic circuit design", US application No: US 13364355, May 2012
  7. A. Belenky, A. Fish, O. Yadid-Pecht and D. Ofer, "Optical pixel and image sensor", PCT application No: PCT/IL2010/000054, July 2010
  8. E. Artyomov, A. Fish, B. Maliatski and O. Yadid-Pecht, “Configurable ASIC-based sensing circuit”, US application No: US11991849, April 2009