library IEEE;
use IEEE.std_logic_1164.all;


entity ser_add is
   port( shiftA , ctr_mux1 , clock , D_in , ctr_mux2 , shiftB , reset : in std_logic ;
          A_out , B_out : out std_logic_vector ( 3 downto 0 )
        );  
  end ser_add;

architecture arc_ser_add of ser_add is
signal s1,s2,s3,s4,s5,s7,s8 : std_logic;

component adder1bit
   port(a,b,cin : in std_logic;
             sum,cout : out std_logic);
 end component;
 
 component dff
    port( d , clk , rst : in std_logic;
         q : out std_logic 
        );
 end component;
 
 component mux1x2
   port ( in0 , in1 : in std_logic; 
  	       ctr : in std_logic ; 
          outp  : out std_logic
         );
end component;

component shiftreg
  port (   shift , clk , din , rst : in std_logic ; 
       	   out4p : out std_logic_vector ( 3 downto 0 ) ;
       	   out1p : out std_logic
       	);   
       	   
end component ;


    
begin
mux1:mux1x2 port map(s1,D_in,ctr_mux1,s3);
mux2:mux1x2 port map(D_in,s2,ctr_mux2,s4);
rgA:shiftreg port map(shiftA,clock,s3,reset,A_out,s5);
rgB:shiftreg port map(shiftB,clock,s4,reset,B_out,s2);
d_ff:dff port map(s8,clock,reset,s7);
adder:adder1bit port map(s5,s2,s7,s1,s8);
end arc_ser_add;

configuration cfg_ser_add of ser_add is
for arc_ser_add
end for;
end cfg_ser_add;
