library IEEE;
use IEEE.std_logic_1164.all;

entity adder1bit is
   port(a,b,cin : in std_logic;
             sum,cout : out std_logic);
 end adder1bit;

architecture arc_adder1bit of adder1bit is 
begin
    sum <= a xor ( b xor cin )  ;   
    cout <= ( a and cin ) or ( b and cin ) or (a and b) ;  
end arc_adder1bit;

configuration cfg_adder1bit of adder1bit is
   for arc_adder1bit
   end for;
end cfg_adder1bit;
