library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
   port( d , clk , rst : in std_logic;
         q : out std_logic 
        );
 end dff;

architecture arc_dff of dff is 
begin
    process ( clk , rst )
    begin
        if ( rst = '1' ) then
            q <= '0';
        elsif ( clk'event and clk='1' ) then
            q <= d ;
       end if ;
    end process ;
end arc_dff;

configuration cfg_dff of dff is
   for arc_dff
   end for;
end cfg_dff;