library IEEE;
use IEEE.std_logic_1164.all;

entity shiftreg_tb is
end shiftreg_tb;

architecture arc_shiftreg_tb of shiftreg_tb is
	type sample is record
	
		shift : std_logic ; 
		clk : std_logic ; 
		din : std_logic ; 
		rst : std_logic ; 
	   out4p : std_logic_vector ( 3 downto 0 ) ;
	   out1p : std_logic ;

	end record;
	
	type sample_array is array (natural range <>) of sample;	
	constant test_data : sample_array :=
		(
--  		 shift    clk  din   rst    out4p  out1p  
	      ('0' , '0', '0' , '1' , "0000" ,'0'),      
 	      ('0' , '1', '0' , '1' , "0000" ,'0'),
 	      
	      ('1' , '0', '1' , '0' , "0000" ,'0'),      
	      ('1' , '1', '1' , '0' , "1000" ,'0'),
	      
	      ('1' , '0', '0' , '0' , "1000" ,'0'),      
	      ('1' , '1', '0' , '0' , "0100" ,'0'),	

	      ('0' , '0', '1' , '0' , "0100" ,'0'),      
	      ('0' , '1', '1' , '0' , "0100" ,'0'),	
	      
	      ('1' , '0', '1' , '0' , "0100" ,'0'),      
	      ('1' , '1', '1' , '0' , "1010" ,'0'),		      

	      ('1' , '0', '1' , '0' , "1010" ,'0'),      
	      ('1' , '1', '1' , '0' , "1101" ,'1'),		
	      
 	      ('1' , '0', '1' , '0' , "1101" ,'1'),      
	      ('1' , '1', '1' , '0' , "1110" ,'0'),		    
                  	       	                   
	      ('1' , '0', '0' , '1' , "0000" ,'0')      		
		);


component shiftreg 
  port (   shift , clk , din , rst : in std_logic ; 
       	   out4p : out std_logic_vector ( 3 downto 0 ) ;
       	   out1p : out std_logic
       	);   
       	   
end component ;
  
     signal shift , clk , din , rst : std_logic ; 
	  signal out4p : std_logic_vector ( 3 downto 0 ) ;
	  signal out1p : std_logic ;
  
     begin
		design: shiftreg port map ( shift , clk , din , rst , out4p , out1p );
		
		process
			begin
				for i in test_data'range loop
					shift <= test_data(i).shift;
					clk <= test_data(i).clk;
					din <= test_data(i).din;
					rst <= test_data(i).rst;
					out4p <= test_data(i).out4p;
					out1p <= test_data(i).out1p;
					wait for 10 ns;
					assert out4p = test_data(i).out4p
						report "output out4p is wrong!"
						severity error;
					assert out1p = test_data(i).out1p
						report "output out1p is wrong!"
						severity error;
				end loop;
	
			wait;			
				
                    end process;		
	      end arc_shiftreg_tb;
	      
configuration cfg_shiftreg_tb of shiftreg_tb is
	for arc_shiftreg_tb
	end for;
end cfg_shiftreg_tb;
