library IEEE;
use IEEE.std_logic_1164.all;


entity mux1x2 is
   port ( in0 , in1 : in std_logic; 
  	       ctr : in std_logic ; 
          outp  : out std_logic
         );
end mux1x2;

architecture arc_mux1x2 of mux1x2 is 
begin
    
    mux: process (in0, in1, ctr)
    begin
          
         if ctr = '0' then   
            outp <= in0;
         else
            outp <= in1;
         end if;
      
    end process mux;    
      
end arc_mux1x2;

configuration cfg_mux1x2 of mux1x2 is
   for arc_mux1x2
   end for;
end cfg_mux1x2;
