
-- Using IEEE STD LOGIC libraries
library IEEE;
use IEEE.std_logic_1164.all;

-- Interface of shiftreg
entity shiftreg is
  port (   shift , clk , din , rst : in std_logic ; 
       	   out4p : out std_logic_vector ( 3 downto 0 ) ;
       	   out1p : out std_logic
       	);   
       	   
end shiftreg ;

-- Component behavior (as a process)
architecture arc_shiftreg of shiftreg is
	
begin
          
    process ( clk, rst )
        
        variable reg_memory : std_logic_vector ( 3 downto 0 );
        
    begin
        
	 if ( rst = '1') then
	        reg_memory := "0000" ;
	   
	 elsif (clk'event and clk = '1') then

	    if shift = '1' then
	         reg_memory(0) := reg_memory(1);
	         reg_memory(1) := reg_memory(2);
	         reg_memory(2) := reg_memory(3);
	         reg_memory(3) := din;
	    end if ;  
	    
	 end if;   
	   
	 out4p <= reg_memory ;
	 out1p <= reg_memory(0) ; 
	   
	   
    end process ;    
      
end arc_shiftreg;

-- Which architecture to use in our circuit
configuration cfg_shiftreg of shiftreg is
   for arc_shiftreg
   end for;
end cfg_shiftreg;
