{"id":5,"date":"2012-04-30T12:29:48","date_gmt":"2012-04-30T12:29:48","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/wimers\/?page_id=5"},"modified":"2023-04-07T15:34:22","modified_gmt":"2023-04-07T12:34:22","slug":"journal-papers","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/wimers\/journal-papers\/","title":{"rendered":"Journal Papers"},"content":{"rendered":"
    \n
  1. Frankel B., Sarfate E., Rossi D. and Wimer S., \"Energy efficiency of opportunistic refreshing for gain-cell embedded DRAM,\u201d IEEE Transactions on Circuits and Systems I , <\/a>Vol. 70, No. 4, Apr 2023, pp. 1605-1612, DOI: <\/a>10.1109\/TCSI.2022.3231866<\/a>.<\/li>\n
  2. Frankel B. and Wimer S., \"A self-refreshable bit-cell for single-cycle refreshing of embedded memories,\u201d IEEE Transactions on Computers , Vol. 72, No. 2, March 2023, pp. 513-519, DOI: 10.1109\/TC.2022.3158481.<\/a><\/li>\n
  3. Halman N. and Wimer S., \"Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions,\u201d Information Processing Letters, Vol. 170, Apr. 2021, DOI: 10.1016\/j.ipl.2021106114.<\/a><\/li>\n
  4. Frankel B., Sarfati E., Wimer S. and Birk Y. , \"Post-silicon analysis of shielded interconnect delays for useful skew clock design,\u201d IEEE Trans. on Electron Devices, Vol. 66, No. 11, Nov. 2019, pp. 4875-4882, DOI: 10.1109\/TED.2019.2938621.<\/a><\/li>\n
  5. Wimer U. and Wimer S., \u201cResource allocation in rooted trees for VLSI applications,\u201d Optimization, Feb. 2019, DOI: 10.1080\/02331934.2019.1576669. <\/a><\/li>\n
  6. Herman R., Frankel B. and Wimer S., \"Optimal queuing-based memory refreshing algorithm for energy efficient processors,\u201d Computers and Electrical Engineering, Vol. 71, Oct 2018, pp. 505-514, DOI: 10.1016\/j.compeleceng.2018.07.057. <\/a><\/li>\n
  7. Sarfati E., Frankel B., Birk Y. and Wimer S., \"Accurate shielded interconnect delay estimation by reconfigurable ring oscillator,\u201d IEEE Trans. on Circuits and Systems I, Vol. 65, No. 10, Oct 2018, pp. 3435-3444, DOI: 10.1109\/TCSI.2018.2825999.<\/a><\/li>\n
  8. Frankel B., Herman R. and Wimer S., \"Queuing-based eDRAM refreshing for ultra-low power processors,\u201d IEEE Trans. on Computers, Vol. 67, No. 9, Sept 2018, pp. 1331-1340, DOI: 10.1109\/TC.2018.2811470.<\/a><\/li>\n
  9. Sarfati E., Frankel B., Birk Y. and Wimer S., \"Optimal VLSI delay tuning by space tapering with clock-tree application,\u201d IEEE Trans. on Circuits and Systems I, Vol. 64, No. 8, Aug 2017, pp. 2160-2170, DOI: 10.1109\/TCSI.2017.2695100.<\/a><\/li>\n
  10. Gluzer D. and Wimer S., \u201cProbability-driven multibit flip-flop integration with clock gating,\u201d IEEE Trans. on VLSI Systems, Vol. 25, No. 3, March 2017, pp. 1173-1177, DOI: 10.1109\/TVLSI.2016.2614004.<\/a><\/li>\n
  11. Kazimirsky A. and Wimer S., \u201cOpportunistic refreshing algorithm for eDRAM memories,\u201d IEEE Trans. on Circuits and Systems I, Vol. 63, No. 11, Nov 2016, pp. 1921-1932, DOI: 10.1109\/TCSI.2016.2600538.<\/a><\/li>\n
  12. Albeck A. and Wimer S., \u201cEnergy efficient computing by multi-mode addition,\u201d Integration \u2013 the VLSI Journal, Vol. 55, 2016, pp. 176-182, DOI: 10.1016\/j.vlsi.2016.06.002.<\/a><\/li>\n
  13. Frankel B. and Wimer S., \u201cOptimal VLSI delay tuning by wire shielding,\u201d Journal of Optimization Theory and Applications, Vol. 170, No. 3, 2016, pp. 1060-1067, DOI: 10.1007\/s10957-016-0960-8.<\/a><\/li>\n
  14. Wimer S., \u201cOptimal weight allocation in rooted trees,\u201d Journal of Combinatorial Optimization, Vol. 31, No. 3, 2016, pp. 1023-1033, DOI 10.1007\/s10878-014-9807-0.<\/a><\/li>\n
  15. Kaplan Y. and Wimer S., \u201cMixing drivers in clock-tree for power supply noise reduction,\u201d IEEE Trans. on Circuits and Systems I, Vol. 62, No. 5, May 2015, pp. 1382-1391, DOI: 10.1109\/TCSI.2015.2411778.<\/a><\/li>\n
  16. Wimer S., \u201cEasy and difficult exact covering problems arising in VLSI power reduction by clock gating,\u201d Discrete Optimization, Vol. 14, 2014, pp. 104-110, DOI 10.1016\/j.disopt.2014.08.004. <\/a><\/li>\n
  17. Levi I., Albeck A., Fish A. and Wimer S., \u201cA low energy and high performance DM2 adder,\u201d IEEE Trans. on Circuits and Systems I, Vol. 61, No. 11, Nov 2014, pp. 3175-3183, DOI 10.1109\/TCSI.2014.2334793. <\/a><\/li>\n
  18. Wimer S. and Stanisavsky A., \u201cEnergy efficient hybrid adder architecture,\u201d Integration \u2013 the VLSI Journal, Vol. 48, 2015, pp. 109-115, DOI 10.1016\/j.vlsi.2014.06.002. <\/a><\/li>\n
  19. Wimer S., Gluzer D. and Wimer U., \u201cUsing well-solvable minimum cost exact covering for VLSI clock energy minimization,\u201d Operations Research Letters, Vol. 42, 2014, pp. 332-336, DOI 10.1016\/j.orl.2014.05.010. <\/a><\/li>\n
  20. Wimer S., Albeck A. and Koren I., \u201cA low energy dual-mode adder,\u201d Computers and Electrical Engineering, Vol. 40, No. 5, July 2014, pp. 1524-1537, DOI 10.1016\/j.compeleceng.2014.04.012. <\/a><\/li>\n
  21. Moiseev K., Wimer S. and Kolodny A., \u201cTiming-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing,\u201d Integration \u2013 the VLSI Journal, Vol. 48, 2015, pp. 116-128, DOI 10.1016\/j.vlsi.2014.03.002.<\/a><\/li>\n
  22. Shaphir E., Pinter R. Y. and Wimer S., \u201cEfficient cell-based migration of VLSI layout ,\u201d Optimization and Engineering, Vol. 16, 2015, pp. 203-223, DOI 10.1007\/s11081-014-9257-7.<\/a><\/li>\n
  23. Shaphir E., Pinter R. Y. and Wimer S., \u201cCell-based interconnect migration by hierarchical optimization,\u201d Integration \u2013 the VLSI Journal, Vol. 47, 2014, pp. 161-174, DOI 10.1016\/j.vlsi.2013.10.003.<\/a><\/li>\n
  24. Wimer S. and Albahari A., \u201cA look-ahead clock gating based on auto-gated flip-flops,\u201d IEEE Trans. on Circuits and Systems I, Vol. 61, No. 5, May 2014, pp. 1465-1472, DOI 10.1109\/TCSI.2013.2289404.<\/a><\/li>\n
  25. Wimer S., \u201cOn optimal flip-flop grouping for VLSI power minimization,\u201d Operations Research Letters, Vol. 41, 2013, pp. 486-489, DOI 10.1016\/j.orl.2013.06.002.<\/a><\/li>\n
  26. Wimer S. and Koren I., \u201cDesign flow for flip-flop grouping in data-driven clock gating,\u201d IEEE Trans. on VLSI Systems, Vol. 22, No. 4, Apr 2014, pp. 771-778, DOI 10.1109\/TVLSI.2013.2253338.<\/a><\/li>\n
  27. Wimer S., \u201cPlanar CMOS to multi-gate layout conversion for maximal fin utilization,\u201d Integration \u2013 the VLSI Journal, Vol. 47, 2014, pp. 115-122, DOI 10.1016\/j.vlsi.2013.03.004.<\/a><\/li>\n
  28. Wimer S. and Koren I., \u201cThe optimal fan-out of clock network for power minimization by adaptive gating,\u201d IEEE Trans. on VLSI Systems,\u00a0Vol. 20, No. 10, Oct 2012, pp. 1772-1780, DOI 10.1109\/TVLSI.2011.2162861.<\/a><\/li>\n
  29. Moiseev K., Kolodny A. and Wimer S., \u201cThe complexity of VLSI power-delay optimization by interconnect resizing,\u201d Journal of Combinatorial Optimization, Vol. 23, No. 2, 2012, pp. 292-300, DOI 10.1007\/s10878-010-9355-1.<\/a><\/li>\n
  30. Emanuel B., Wimer S. and Wolansky G., \u201cUsing well-solvable quadratic assignment problems for VLSI interconnect applications,\u201d Discrete Applied Mathematics, Vol. 160, No. 4-5, 2012, pp. 525-535, DOI 10.1016\/j.dam.2011.11.017.<\/a><\/li>\n
  31. E. Cela, N. S. Schmuck, S. Wimer and G. J. Woeginger, \u201cThe Wiener maximum quadratic assignment problem,\u201d Discrete Optimization, No. 8, 2011, pp. 411-416.<\/a><\/li>\n
  32. Wimer S., Moiseev K. and Kolodny A., \u201cOn VLSI interconnect optimization and linear ordering problem,\u201d Optimization and Engineering, No. 12, 2011, pp. 603-609. <\/a><\/li>\n
  33. Moiseev K., Kolodny A. and Wimer S., \u201cInterconnect bundle sizing under discrete dsign rules\u201d, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 29, No. 10, Oct. 2010, pp. 1650 \u2013 1654.<\/a><\/li>\n
  34. Moiseev, K., Kolodny A. and Wimer S., \u201cPower-delay optimization in VLSI microprocessors by wire spacing,\u201d ACM Trans. on Design Automation of Electronic Systems, Vol. 14, No. 4, Aug 2009, Article No. 55.<\/a><\/li>\n
  35. Moiseev K., Kolodny K. and Wimer S., \u201cTiming-aware power-optimal ordering of signals,\u201d ACM Trans. on Design Automation of Electronic Systems, Vol. 13, No. 4, Sept 2008, Article No. 65. <\/a><\/li>\n
  36. Moiseev K., Wimer S. and Kolodny A., \u201cOn optimal ordering of signals in parallel wire bundles,\u201d Integration \u2013 the VLSI Journal, Vol. 41, 2008, pp. 253 \u2013 268.<\/a><\/li>\n
  37. Wimer S., Michaely S., Moiseev K. and Kolodny A., \u201cOptimal bus sizing in migration of processor design,\u201d IEEE Trans. on Circuits and Systems - I, 2006, pp. 1089 \u2013 1100.<\/a><\/li>\n
  38. Feldman J. A., Wagner I. A. and Wimer S., \u201cAn efficient algorithm for some multirow layout problems,\u201d IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, pp. 1178 \u2013 1185.<\/a><\/li>\n
  39. Wimer S., Cederbaum I and Koren I., \u201cOn paths with the shortest average arc length in weighted graphs,\u201d Discrete Applied Mathematics, 1993, pp. 169 \u2013 179.<\/a><\/li>\n
  40. Cederbaum I., Koren I. And Wimer S., \u201cBalanced block spacing for VLSI layout,\u201d Discrete Applied Mathematics, 1992, pp. 303 \u2013 318.<\/a><\/li>\n
  41. Bar-Yehuda R., Feldman J. A., Pinter R. Y. and Wimer S., \u201cDepth-first-search and dynamic programming algorithms for efficient CMOS cell generation,\u201d IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, pp. 737 \u2013 743.<\/a><\/li>\n
  42. Wimer S., Koren I. And Cederbaum I., \u201cOptimal aspect ratios of building blocks in VLSI,\u201d IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, pp. 139 \u2013 145.<\/a><\/li>\n
  43. Wimer S., Koren I. and Cederbaum I., \u201cFloorplans, planar graphs and layouts,\u201d IEEE Trans. on Circuits and Systems, 1988, pp. 267 \u2013 278.<\/a><\/li>\n
  44. Wimer S. and Koren I., \u201cAnalysis of strategies for constructive general block placement,\u201d IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, pp. 371 \u2013 377.<\/a><\/li>\n
  45. Wimer S., Pinter R. Y. and Feldman J. A., \u201cOptimal chaining of CMOS transistors in functional cell,\u201d IEEE Tran. on CAD of Integrated Circuits and Systems, 1987, pp. 795 \u2013 801.<\/a><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

    Frankel B., Sarfate E., Rossi D. and Wimer S., “Energy efficiency of opportunistic refreshing for gain-cell embedded DRAM,\u201d IEEE Transactions on Circuits and Systems I , Vol. 70, No. 4, Apr 2023, pp. 1605-1612, DOI: 10.1109\/TCSI.2022.3231866. Frankel B. and Wimer S., “A self-refreshable bit-cell for single-cycle refreshing of embedded memories,\u201d IEEE Transactions on Computers , … Continue reading Journal Papers<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":14,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-5","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/5"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/users\/14"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/comments?post=5"}],"version-history":[{"count":126,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/5\/revisions"}],"predecessor-version":[{"id":1240,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/5\/revisions\/1240"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/media?parent=5"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}