{"id":45,"date":"2012-05-07T18:13:05","date_gmt":"2012-05-07T15:13:05","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/wimers\/?page_id=45"},"modified":"2019-11-25T01:42:34","modified_gmt":"2019-11-24T23:42:34","slug":"conference-papers","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/wimers\/conference-papers\/","title":{"rendered":"Conference Papers"},"content":{"rendered":"
    \n
  1. Wimer S. and Koren I., \u201cEnergy efficient deeply fused dot-product multiplication architecture,\u201d 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 115-122, July 2016.<\/a><\/li>\n
  2. Wimer S., Stanislavsky A. and Kolodny A., \u201cEnergy efficient addition by two-sided carry-reverse computation,\u201d IEEE 27th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2012.<\/a><\/li>\n
  3. Kaplan Y.\u00a0and Wimer S., \u201cPost optimization of a clock tree for power supply noise reduction,\u201d IEEE 27th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2012.<\/a><\/li>\n
  4. Ran Manevich, Israel Cidon, Avinoam Kolodny, Isaskhar Walter and Shmuel Wimer, \u201cA cost effective centralized adaptive routing for networks-on-chip,\u201d 14th EUROMICRO Conference on Digital System Design, Aug 2011, pp. 39-46.<\/a><\/li>\n
  5. Cohen I., Koren I. and Wimer S., \u201cAdaptive clock gating for shift register based circuits,\u201d IEEE 26th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2010.<\/a><\/li>\n
  6. Moiseev K., Kolodny A., and Wimer S., \u201cInterconnect power and delay optimization by dynamic programming in gridded design rules,\u201d International Symposium on Physical Design \u2013 ISPD, March 2010.<\/a><\/li>\n
  7. Moiseev K., Wimer S. and Kolodny A., \u201cPower saving in CMOS processors by optimal wire spacing,\u201d IFIP\/IEEE Intl. Conf. on VLSI - VLSI SoC 2008.<\/li>\n
  8. K. Moiseev, S. Wimer and A. Kolodny, \"Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing\", Proceedings of International Symposium on Circuits and Systems, pp. 329-332, May 2006.<\/li>\n
  9. Michaely S., Wimer S. and Kolodny A., \u201cOptimal resizing of bus wires in layout migration,\u201d ICECS2004 - IEEE 11th International Conference on Electronics, Circuits, and Systems, 2004, pp 411-414.<\/li>\n
  10. Cohen U., Grishchenko L., Nitzan R., Topaz M. and Wimer S., \u201cAMPS and SiClone integration for design migration of Banias microprocessor,\u201d DTTC, Intel Design Technology and Testing Conference, July 2002.<\/li>\n
  11. Nitzan R. and Wimer S., \u201cAMPS and SiClone integration for implementing 0.18u to 0.13u design migration\u201d, SNUG \u2013 Synopsys Users Group, San Jose, March 2002.<\/li>\n
  12. Feldman J. A., Wagner I. A. and Wimer S., \u201cAn efficient algorithm for some multirow layout problems,\u201d Proceedings of the MCNC Workshop on VLSI Layout, 1992.<\/li>\n
  13. Solel E. and Wimer S., \u201cBreathing maze router for analog VLSI cell generation,\u201d Proceedings of the International Conference on CAD\/CAM and AMT, 1989.<\/li>\n
  14. Bar-Yehuda R., Feldman J. A., Medan Y., Turgeman A. and Wimer S., \u201cIntegrated image design and complex standard CMOS cell generator,\u201d IEEE 16th Conference of Electrical and Electronics Engineers in Israel, 1988.<\/li>\n
  15. Wimer S., Cederbaum I. and Koren I., \u201cOptimal aspect ratios of building blocks in VLSI,\u201d Proceedings of the 25th ACM\/IEEE Design Automation Conference, 1988, pp. 66 \u2013 72.<\/li>\n
  16. Bar-Yehuda R., Feldman J. A., Pinter R. Y. and Wimer S., \u201cDepth-first-search and dynamic programming algorithms for efficient CMOS cell generation,\u201d Proceedings of the 5th MIT VLSI Conference, 1989, pp. 66 \u2013 72.<\/li>\n
  17. Wimer S., Cederbaum I. and Koren I., \u201cOptimal aspect ratios of building blocks in VLSI,\u201d Abstracts of 22nd General Assembly of URSI, 1987.<\/li>\n
  18. Feldman J. A., Pinter R. Y. and Wimer S., \u201cAn optimal cell generation and composition system,\u201d IEEE 15th Conference of Electrical and Electronics Engineers in Israel, 1987.<\/li>\n
  19. Wimer S. and Koren I., \u201cConstructive placement of general blocks in VLSI under uncertainties in the position of ports,\u201d ICCAD86 \u2013 IEEE International Conference on CAD, 1986, pp. 458 \u2013 461.<\/li>\n
  20. Wimer S., Pinter R. Y. and Feldman J. A., \u201cOptimal chaining of CMOS transistors in functional cell,\u201d ICCAD86 \u2013 IEEE International Conference on CAD, 1986, pp. 66 \u2013 69.<\/li>\n
  21. Wimer S. and Sharfman N., \u201cHOPLA \u2013 PLA optimization and synthesis,\u201d in Proceedings of the 20th ACM\/IEEE Design Automation Conference, 1983, pp. 790 \u2013 794.<\/a><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

    Wimer S. and Koren I., \u201cEnergy efficient deeply fused dot-product multiplication architecture,\u201d 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 115-122, July 2016. Wimer S., Stanislavsky A. and Kolodny A., \u201cEnergy efficient addition by two-sided carry-reverse computation,\u201d IEEE 27th Convention of Electrical and Electronics Engineers in Israel (IEEEI), Nov. 2012. … Continue reading Conference Papers<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-45","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/45"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/comments?post=45"}],"version-history":[{"count":29,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/45\/revisions"}],"predecessor-version":[{"id":910,"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/pages\/45\/revisions\/910"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/wimers\/wp-json\/wp\/v2\/media?parent=45"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}