![\"\"](\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2023\/06\/Intel-logo-2022-300x122.png\")
<\/a><\/strong><\/span>Preparation of these recorded
lectures was kindly supported by Intel.<\/strong><\/span><\/h4>\n\u00a0<\/p>\n
\n- All of my Kahoots can be found under my profile on Kahoot.com<\/a><\/li>\n<\/ul>\n
\n- Introduction\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 1a: Introduction<\/a><\/li>\n
- Section 1b: Building a Chip<\/a><\/li>\n
- Section 1c: Design Automation<\/a><\/li>\n
- Section 1d: The Chip Design Flow<\/a><\/li>\n
- Kahoot! for discussing Lecture 1\u00a0<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 1a<\/a>, 1b<\/a>, 1c<\/a>, 1d<\/a><\/li>\n<\/ul>\n<\/li>\n
- Verilog (Synthesizeable RTL)\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 2a: Verilog<\/a><\/li>\n
- Section 2b: Verilog Syntax<\/a><\/li>\n
- Section 2c: Simple Verilog Examples<\/a><\/li>\n
- Section 2d: Verilog FSM Implementation<\/a><\/li>\n
- Section 2e: Coding Style for RTL - part 1\u00a0<\/a><\/li>\n
- Supplementary Material<\/span>: Writing Synthesizeable RTL<\/a> (Slides<\/a>)<\/li>\n
- Kahoot! for discussing Lecture 2<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 2a<\/a>, 2b<\/a>, 2c<\/a>, 2d<\/a>, 2e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Logic Synthesis - Part I (Standard Cell Libraries)\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 3a: Logic Synthesis - Part 1<\/a><\/li>\n
- Section3b: HDL Compilation<\/a><\/li>\n
- Section 3c: Library Definition<\/a><\/li>\n
- Section 3d: LEF<\/a><\/li>\n
- Section 3e: Liberty (.lib)<\/a><\/li>\n
- Section 3f: Contents of Standard Cell Libraries<\/a><\/li>\n
- Kahoot! for discussing Lecture 3<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Use English Version Slides<\/em>): Section 3a<\/a>, 3b<\/a>, 3c<\/a>, 3d<\/a>, 3e<\/a>, 3f<\/a><\/li>\n<\/ul>\n<\/li>\n
- Logic Synthesis - Part II (Elaboration and Technology Mapping)\n
\n- English\u00a0 (Accompanying Slides<\/a>)\n
\n- Section 4a: Logic Synthesis - Part 2<\/a><\/li>\n
- Section 4b: BDDs and Boolean Minimization<\/a><\/li>\n
- Section 4c: Constraint Definition<\/a><\/li>\n
- Section 4d: Technology Mapping<\/a><\/li>\n
- Section 4e: Verilog for Synthesis - revisited<\/a><\/li>\n
- Section 4f: Timing Optimization<\/a><\/li>\n
- Kahoot! for discussing Lecture 4<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea (Use English Version Slides<\/em>): Section 4a<\/a>, 4b<\/a>, 4c<\/a>, 4d<\/a>, 4e<\/a>, 4f<\/a><\/li>\n<\/ul>\n<\/li>\n
- Static Timing Analysis (STA)\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 5a: Timing Analysis<\/a><\/li>\n
- Section 5b: Timing Constraints<\/a><\/li>\n
- Section 5c: Static Timing Analysis (STA)<\/a><\/li>\n
- Section 5d: STA Example<\/a><\/li>\n
- Section 5e: Design Constraints (SDC)<\/a><\/li>\n
- Section 5f: SDC Continued<\/a><\/li>\n
- Section 5g: Timing Reports<\/a><\/li>\n
- Section 5h: Multi-Mode Multi-Corner (MMMC)\u00a0<\/a><\/li>\n
- Kahoot! for discussing Lecture 5<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Sections 5a-b<\/a>, 5c-d<\/a>, 5e-f<\/a>, 5g<\/a>, 5h<\/a><\/li>\n<\/ul>\n<\/li>\n
- Moving to the Physical Domain (incl. Floorplan)\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 6a: Moving to the Physical Domain<\/a><\/li>\n
- Section 6b: Multiple Voltage Domains<\/a><\/li>\n
- Section 6c: Floorplanning<\/a><\/li>\n
- Section 6d: Hierarchical Design<\/a><\/li>\n
- Section 6e: Power Planning<\/a><\/li>\n
- Kahoot! for discussing Lecture 6<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 6a<\/a>, 6b<\/a>, 6c<\/a>, 6d<\/a>, 6e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Standard Cell Placement\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 7a: Standard Cell Placement<\/a><\/li>\n
- Section 7b: Random Placement<\/a><\/li>\n
- Section 7c: Analytic Placement<\/a><\/li>\n
- Section 7d: Analytic Placement Example<\/a><\/li>\n
- Section 7e: Placement in Practice<\/a><\/li>\n
- Kahoot! for discussing Lecture 7<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 7a<\/a>, 7b<\/a>, 7c<\/a>, 7d<\/a>, 7e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Clock Tree Synthesis\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 8a: Clock Tree Synthesis (CTS)<\/a><\/li>\n
- Section 8b: Clock Distribution<\/a><\/li>\n
- Section 8c: Clock Concurrent Optimization (CCOpt)<\/a><\/li>\n
- Section 8d: Clock Tree Synthesis in EDA Tools<\/a><\/li>\n
- Section 8e: Clock Routing and Clock Tree Analysis<\/a><\/li>\n
- Section 8f: Clock Generation<\/a><\/li>\n
- Section 8g: Clock Domain Crossing (CDC)<\/a><\/li>\n
- Kahoot! for discussing Lecture 8<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 8a<\/a>, 8b-c<\/a>, 8d<\/a>, 8e<\/a>\u00a0(Sections 8f and 8g only in English)<\/li>\n<\/ul>\n<\/li>\n
- Gobal and Detailed Routing\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 9a: Routing<\/a><\/li>\n
- Section 9b: Maze Routing<\/a><\/li>\n
- Section 9c: Maze Routing (continued)<\/a><\/li>\n
- Section 9d: Routing in Practice<\/a><\/li>\n
- Section 9e: Signal Integrity (SI) and Design for Manufacturing (DFM)<\/a><\/li>\n
- Kahoot! for discussing Lecture 9<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 9a<\/a>, 9b<\/a>, 9c<\/a>, 9d<\/a>, 9e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Input\/Output Circuits and Packaging\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 10a: Packaging<\/a><\/li>\n
- Section 10b: I\/O Circuits - Digital IOs<\/a><\/li>\n
- Section 10c: I\/O Circuits - Analog IOs, ESD Protection, Pad Configurations<\/a><\/li>\n
- Section 10d: System-in-Package (SiP)<\/a><\/li>\n
- Kahoot! for discussing Lecture 10<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 10a<\/a>, 10b<\/a>, 10c<\/a> (Section 10d only in English)<\/li>\n<\/ul>\n<\/li>\n
- Chip Finishing and Sign-Off\n
\n- English\u00a0 (Slides<\/a>)\n
\n- Section 11a: Sign-off Timing<\/a><\/li>\n
- Section 11b: Additional issues in Sign-off Timing<\/a><\/li>\n
- Section 11c: Chip Finishing, including Density Fill and Antenna Fixes<\/a><\/li>\n
- Section 11d: Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC\/LVS\/ERC<\/a><\/li>\n
- Kahoot! for discussing Lecture 11<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 11a-b<\/a>, 11c-d<\/a> (Note that English version is more extensive)<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n
\u00a0<\/p>\n\n\n<\/p>\n
\u00a0<\/h3>\n\u00a0<\/h3>\nAdditional Material:<\/h2>\nDigital-on-top Physical Verification (Fullchip LVS\/DRC)\u00a0<\/h3>\n
\n\n\n\n<\/p>\n
\n- \n
\n- Slides<\/a><\/li>\n
- Video Playlist<\/a>\n
\n- Part 1: Introduction to Digital-on-Top LVS<\/a><\/li>\n
- Part 2: Creating the LVS-ready Verilog Netlist<\/a><\/li>\n
- Part 3: Translating the Verilog netlist into SPICE<\/a><\/li>\n
- Part 4: Extracting the LVS-ready Layout netlist<\/a><\/li>\n
- Part 5: Running LVS comparison<\/a><\/li>\n
- Part 6: Fullchip DRC and Chip Finishing<\/a><\/li>\n<\/ul>\n<\/li>\n
- \n
- Introduction\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 1a: Introduction<\/a><\/li>\n
- Section 1b: Building a Chip<\/a><\/li>\n
- Section 1c: Design Automation<\/a><\/li>\n
- Section 1d: The Chip Design Flow<\/a><\/li>\n
- Kahoot! for discussing Lecture 1\u00a0<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 1a<\/a>, 1b<\/a>, 1c<\/a>, 1d<\/a><\/li>\n<\/ul>\n<\/li>\n
- Verilog (Synthesizeable RTL)\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 2a: Verilog<\/a><\/li>\n
- Section 2b: Verilog Syntax<\/a><\/li>\n
- Section 2c: Simple Verilog Examples<\/a><\/li>\n
- Section 2d: Verilog FSM Implementation<\/a><\/li>\n
- Section 2e: Coding Style for RTL - part 1\u00a0<\/a><\/li>\n
- Supplementary Material<\/span>: Writing Synthesizeable RTL<\/a> (Slides<\/a>)<\/li>\n
- Kahoot! for discussing Lecture 2<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 2a<\/a>, 2b<\/a>, 2c<\/a>, 2d<\/a>, 2e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Logic Synthesis - Part I (Standard Cell Libraries)\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 3a: Logic Synthesis - Part 1<\/a><\/li>\n
- Section3b: HDL Compilation<\/a><\/li>\n
- Section 3c: Library Definition<\/a><\/li>\n
- Section 3d: LEF<\/a><\/li>\n
- Section 3e: Liberty (.lib)<\/a><\/li>\n
- Section 3f: Contents of Standard Cell Libraries<\/a><\/li>\n
- Kahoot! for discussing Lecture 3<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Use English Version Slides<\/em>): Section 3a<\/a>, 3b<\/a>, 3c<\/a>, 3d<\/a>, 3e<\/a>, 3f<\/a><\/li>\n<\/ul>\n<\/li>\n
- Logic Synthesis - Part II (Elaboration and Technology Mapping)\n
- \n
- English\u00a0 (Accompanying Slides<\/a>)\n
- \n
- Section 4a: Logic Synthesis - Part 2<\/a><\/li>\n
- Section 4b: BDDs and Boolean Minimization<\/a><\/li>\n
- Section 4c: Constraint Definition<\/a><\/li>\n
- Section 4d: Technology Mapping<\/a><\/li>\n
- Section 4e: Verilog for Synthesis - revisited<\/a><\/li>\n
- Section 4f: Timing Optimization<\/a><\/li>\n
- Kahoot! for discussing Lecture 4<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea (Use English Version Slides<\/em>): Section 4a<\/a>, 4b<\/a>, 4c<\/a>, 4d<\/a>, 4e<\/a>, 4f<\/a><\/li>\n<\/ul>\n<\/li>\n
- Static Timing Analysis (STA)\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 5a: Timing Analysis<\/a><\/li>\n
- Section 5b: Timing Constraints<\/a><\/li>\n
- Section 5c: Static Timing Analysis (STA)<\/a><\/li>\n
- Section 5d: STA Example<\/a><\/li>\n
- Section 5e: Design Constraints (SDC)<\/a><\/li>\n
- Section 5f: SDC Continued<\/a><\/li>\n
- Section 5g: Timing Reports<\/a><\/li>\n
- Section 5h: Multi-Mode Multi-Corner (MMMC)\u00a0<\/a><\/li>\n
- Kahoot! for discussing Lecture 5<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Sections 5a-b<\/a>, 5c-d<\/a>, 5e-f<\/a>, 5g<\/a>, 5h<\/a><\/li>\n<\/ul>\n<\/li>\n
- Moving to the Physical Domain (incl. Floorplan)\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 6a: Moving to the Physical Domain<\/a><\/li>\n
- Section 6b: Multiple Voltage Domains<\/a><\/li>\n
- Section 6c: Floorplanning<\/a><\/li>\n
- Section 6d: Hierarchical Design<\/a><\/li>\n
- Section 6e: Power Planning<\/a><\/li>\n
- Kahoot! for discussing Lecture 6<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 6a<\/a>, 6b<\/a>, 6c<\/a>, 6d<\/a>, 6e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Standard Cell Placement\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 7a: Standard Cell Placement<\/a><\/li>\n
- Section 7b: Random Placement<\/a><\/li>\n
- Section 7c: Analytic Placement<\/a><\/li>\n
- Section 7d: Analytic Placement Example<\/a><\/li>\n
- Section 7e: Placement in Practice<\/a><\/li>\n
- Kahoot! for discussing Lecture 7<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 7a<\/a>, 7b<\/a>, 7c<\/a>, 7d<\/a>, 7e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Clock Tree Synthesis\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 8a: Clock Tree Synthesis (CTS)<\/a><\/li>\n
- Section 8b: Clock Distribution<\/a><\/li>\n
- Section 8c: Clock Concurrent Optimization (CCOpt)<\/a><\/li>\n
- Section 8d: Clock Tree Synthesis in EDA Tools<\/a><\/li>\n
- Section 8e: Clock Routing and Clock Tree Analysis<\/a><\/li>\n
- Section 8f: Clock Generation<\/a><\/li>\n
- Section 8g: Clock Domain Crossing (CDC)<\/a><\/li>\n
- Kahoot! for discussing Lecture 8<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea\u00a0 (Slides<\/a>): Section 8a<\/a>, 8b-c<\/a>, 8d<\/a>, 8e<\/a>\u00a0(Sections 8f and 8g only in English)<\/li>\n<\/ul>\n<\/li>\n
- Gobal and Detailed Routing\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 9a: Routing<\/a><\/li>\n
- Section 9b: Maze Routing<\/a><\/li>\n
- Section 9c: Maze Routing (continued)<\/a><\/li>\n
- Section 9d: Routing in Practice<\/a><\/li>\n
- Section 9e: Signal Integrity (SI) and Design for Manufacturing (DFM)<\/a><\/li>\n
- Kahoot! for discussing Lecture 9<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 9a<\/a>, 9b<\/a>, 9c<\/a>, 9d<\/a>, 9e<\/a><\/li>\n<\/ul>\n<\/li>\n
- Input\/Output Circuits and Packaging\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 10a: Packaging<\/a><\/li>\n
- Section 10b: I\/O Circuits - Digital IOs<\/a><\/li>\n
- Section 10c: I\/O Circuits - Analog IOs, ESD Protection, Pad Configurations<\/a><\/li>\n
- Section 10d: System-in-Package (SiP)<\/a><\/li>\n
- Kahoot! for discussing Lecture 10<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 10a<\/a>, 10b<\/a>, 10c<\/a> (Section 10d only in English)<\/li>\n<\/ul>\n<\/li>\n
- Chip Finishing and Sign-Off\n
- \n
- English\u00a0 (Slides<\/a>)\n
- \n
- Section 11a: Sign-off Timing<\/a><\/li>\n
- Section 11b: Additional issues in Sign-off Timing<\/a><\/li>\n
- Section 11c: Chip Finishing, including Density Fill and Antenna Fixes<\/a><\/li>\n
- Section 11d: Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC\/LVS\/ERC<\/a><\/li>\n
- Kahoot! for discussing Lecture 11<\/a><\/li>\n<\/ul>\n<\/li>\n
- \u05e2\u05d1\u05e8\u05d9\u05ea<\/a>\u00a0 (Slides<\/a>): Section 11a-b<\/a>, 11c-d<\/a> (Note that English version is more extensive)<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n
\u00a0<\/p>\n\n\n<\/p>\n
\u00a0<\/h3>\n
\u00a0<\/h3>\n
Additional Material:<\/h2>\n
Digital-on-top Physical Verification (Fullchip LVS\/DRC)\u00a0<\/h3>\n
\n\n\n\n<\/p>\n
- \n
- \n
- \n
- Slides<\/a><\/li>\n
- Video Playlist<\/a>\n
- \n
- Part 1: Introduction to Digital-on-Top LVS<\/a><\/li>\n
- Part 2: Creating the LVS-ready Verilog Netlist<\/a><\/li>\n
- Part 3: Translating the Verilog netlist into SPICE<\/a><\/li>\n
- Part 4: Extracting the LVS-ready Layout netlist<\/a><\/li>\n
- Part 5: Running LVS comparison<\/a><\/li>\n
- Part 6: Fullchip DRC and Chip Finishing<\/a><\/li>\n<\/ul>\n<\/li>\n
- Part 2: Creating the LVS-ready Verilog Netlist<\/a><\/li>\n
- Video Playlist<\/a>\n
- Slides<\/a><\/li>\n
- Section 11b: Additional issues in Sign-off Timing<\/a><\/li>\n
- Section 11a: Sign-off Timing<\/a><\/li>\n
- Section 10b: I\/O Circuits - Digital IOs<\/a><\/li>\n
- Section 10a: Packaging<\/a><\/li>\n
- Section 9b: Maze Routing<\/a><\/li>\n
- Section 9a: Routing<\/a><\/li>\n
- Section 8b: Clock Distribution<\/a><\/li>\n
- Section 8a: Clock Tree Synthesis (CTS)<\/a><\/li>\n
- Section 7b: Random Placement<\/a><\/li>\n
- Section 7a: Standard Cell Placement<\/a><\/li>\n
- Section 6b: Multiple Voltage Domains<\/a><\/li>\n
- Section 6a: Moving to the Physical Domain<\/a><\/li>\n
- Section 5b: Timing Constraints<\/a><\/li>\n
- Section 5a: Timing Analysis<\/a><\/li>\n
- Section 4b: BDDs and Boolean Minimization<\/a><\/li>\n
- Section 4a: Logic Synthesis - Part 2<\/a><\/li>\n
- Section3b: HDL Compilation<\/a><\/li>\n
- Section 3a: Logic Synthesis - Part 1<\/a><\/li>\n
- Section 2b: Verilog Syntax<\/a><\/li>\n
- Section 2a: Verilog<\/a><\/li>\n
- Section 1b: Building a Chip<\/a><\/li>\n
- Section 1a: Introduction<\/a><\/li>\n
- English\u00a0 (Slides<\/a>)\n