{"id":652,"date":"2021-04-11T12:46:44","date_gmt":"2021-04-11T09:46:44","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/temanad\/?page_id=652"},"modified":"2022-04-02T21:26:13","modified_gmt":"2022-04-02T18:26:13","slug":"other-vlsi-eda-lectures","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/temanad\/other-vlsi-eda-lectures\/","title":{"rendered":"Other VLSI\/EDA Lectures"},"content":{"rendered":"\n<h3 class=\"wp-block-heading\">Digital-on-top Physical Verification (Fullchip LVS\/DRC)&nbsp;<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2020\/09\/Full-Chip-DRC-LVS-slides.pdf\">Slides<\/a><\/li><li><a href=\"https:\/\/www.youtube.com\/playlist?list=PLZU5hLL_713xp5sDexQMVdOM86l_wP5w8\">Video Playlist<\/a><ul><li><a href=\"https:\/\/youtu.be\/Hq6QD8aX2Q0\">Part 1: Introduction to Digital-on-Top LVS<\/a><\/li><li><a href=\"https:\/\/youtu.be\/soaMWQZzEW0\">Part 2: Creating the LVS-ready Verilog Netlist<\/a><\/li><li><a href=\"https:\/\/youtu.be\/Nr9gSGkh8gs\">Part 3: Translating the Verilog netlist into SPICE<\/a><\/li><li><a href=\"https:\/\/youtu.be\/2pJBEaqHYXI\">Part 4: Extracting the LVS-ready Layout netlist<\/a><\/li><li><a href=\"https:\/\/youtu.be\/827KkWIINus\">Part 5: Running LVS comparison<\/a><\/li><li><a href=\"https:\/\/youtu.be\/mqtD_ADwt1s\">Part 6: Fullchip DRC and Chip Finishing<\/a><\/li><\/ul><\/li><li>Supplement: <a href=\"https:\/\/youtu.be\/3U0rEDy4qrY\">Custom Block Preparation for Digital-on-Top Integration<\/a> (<a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2021\/12\/Preparing-a-block-for-Digital-on-Top-Integration.pdf\">Slides<\/a>)<\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Behind the Scenes of the SPICE Circuit Simulator<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2022\/04\/Lecture-3-Behind-the-scenes-of-SPICE.pdf\">Slides <\/a>(English Only)<\/li><li>Video recordings:<\/li><\/ul>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/1ZhzhWAt7xc\">Part 1: Introduction<\/a><\/li><li><a href=\"https:\/\/youtu.be\/Zk0y4J8y9nY\">Part 2: DC Analysis<\/a><\/li><li><a href=\"https:\/\/youtu.be\/PrYmqYbrJLA\">Part 3: The Newton-Raphson Method<\/a><\/li><li><a href=\"https:\/\/youtu.be\/EEahNnLI4AI\">Part 4: AC Analysis, Transient Analysis<\/a><\/li><li><a href=\"https:\/\/youtu.be\/hF0yXFxtqyk\">Part 5: Other Stuff<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">RISC-V for Embedded Systems:\u00a0A First Introduction<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/xUn_FWVqNeU\">Video<\/a><\/li><li><a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2019\/11\/RISC-V-Intro-for-Hackathon.pdf\">Slides<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Power Intent and Low Power Methodology<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/TKfV73i-0RY\">Video&nbsp;<\/a><\/li><li><a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2020\/06\/Power-Intent-and-Low-Power-Methodology.pdf\">Slides<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Design For Test<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/P21K-Db4VWU\">Video<\/a><\/li><li><a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2020\/06\/DFT-Lecture.pdf\">Slides<\/a>&nbsp; &nbsp;<\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Research Talks<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/h8cnHChBl1A\">Gain-Cell embedded DRAM: An alternative option for embedded memories<\/a> (<a href=\"http:\/\/www.eng.biu.ac.il\/temanad\/files\/2021\/10\/GC-eDRAM-Overview-10-2021.pdf\">Slides<\/a>)<\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Additional VLSI\/EDA Stuff<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li>Gain-Cell embedded DRAM<\/li><li><a href=\"https:\/\/youtu.be\/41oU5Tcz4SQ\">TCLPY - Interfacing Python with your EDA Tools - Udi Kra<\/a><\/li><li><a href=\"https:\/\/youtu.be\/cb7aHtkrz8o\">Abstract Generation (LEF\/LIB) for Custom Blocks - Odem Harel<\/a><\/li><li><a href=\"https:\/\/youtu.be\/dpwk0exN47I\">OpenRAM - Esteban Garzon<\/a><\/li><li><a href=\"https:\/\/youtu.be\/t3Ndg5bsxZU\">Efficient CNN with xPulp Extensions - Udi Kra<\/a><\/li><\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">Student Presentations<\/h3>\n\n\n\n<ul class=\"wp-block-list\"><li><a href=\"https:\/\/youtu.be\/exzg26oGvb8\">RISC-V - Hisham Nijem<\/a><\/li><li><a href=\"https:\/\/zoom.us\/rec\/share\/uuxpJaHr2kFIRYmU-l79BrV7WbTfX6a8h3MZ-fFZnR5sivOqq7vghOjJTD4nChhZ\">Power-on-Reset<\/a> - <a href=\"https:\/\/zoom.us\/rec\/share\/uuxpJaHr2kFIRYmU-l79BrV7WbTfX6a8h3MZ-fFZnR5sivOqq7vghOjJTD4nChhZ\">Assaf Feldman<\/a><\/li><li><a href=\"https:\/\/zoom.us\/rec\/share\/-cVnFb7ZyFlIAdL_y32PRYo9L9TDaaa813UX_vRcz0rU0LLjsdlclg5kbUvsg57l\">Neural Network on an FPGA<\/a> - <a href=\"https:\/\/zoom.us\/rec\/share\/-cVnFb7ZyFlIAdL_y32PRYo9L9TDaaa813UX_vRcz0rU0LLjsdlclg5kbUvsg57l\">Yosi Greenblatt<\/a><\/li><li><\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Digital-on-top Physical Verification (Fullchip LVS\/DRC)&nbsp; Slides Video Playlist Part 1: Introduction to Digital-on-Top LVS Part 2: Creating the LVS-ready Verilog Netlist Part 3: Translating the Verilog netlist into SPICE Part 4: Extracting the LVS-ready Layout netlist Part 5: Running LVS comparison Part 6: Fullchip DRC and Chip Finishing Supplement: Custom Block Preparation for Digital-on-Top Integration &hellip; <a href=\"https:\/\/www.eng.biu.ac.il\/temanad\/other-vlsi-eda-lectures\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Other VLSI\/EDA Lectures<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":61,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-652","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/652"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/users\/61"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/comments?post=652"}],"version-history":[{"count":8,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/652\/revisions"}],"predecessor-version":[{"id":968,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/652\/revisions\/968"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/media?parent=652"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}