{"id":51,"date":"2015-10-28T15:22:25","date_gmt":"2015-10-28T13:22:25","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/temanad\/?page_id=51"},"modified":"2019-05-07T17:23:18","modified_gmt":"2019-05-07T14:23:18","slug":"research-tapeouts","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/temanad\/research-tapeouts\/","title":{"rendered":"Research Tapeouts"},"content":{"rendered":"<p><strong>2019 -\u00a0SoC2<\/strong><br \/>\nSystem-on-Chip<\/p>\n<ul>\n<li>Technology: TSMC 16FFC<\/li>\n<li>Co-academic director and leader of GC-eDRAM block<\/li>\n<\/ul>\n<p><strong>2018 -\u00a0Kwak<\/strong><br \/>\nGain Cell eDRAM Test Chip and more<\/p>\n<ul>\n<li>Technology: Samsung 28nm FD-SOI<\/li>\n<li>Project Manager<\/li>\n<\/ul>\n<p><strong>2017 -\u00a0Martini<\/strong><br \/>\nGain Cell eDRAM Test Chip and more<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Project Manager<\/li>\n<\/ul>\n<p><strong>2016 -\u00a0BEER<\/strong><br \/>\nGain Cell eDRAM Test Chip and more<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Project Manager<\/li>\n<\/ul>\n<p><strong>2016 -\u00a0DAFNA<\/strong><br \/>\nGain Cell eDRAM Test Chip<\/p>\n<ul>\n<li>Technology: TSMC 28nm<\/li>\n<li>First GC-eDRAM test chip in a 28nm bulk technology, designed in collaboration with Mellanox.<\/li>\n<li>Project Manager<\/li>\n<\/ul>\n<p><strong>2016 - Polar Bear<\/strong><br \/>\nPolar Decoder chip<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Advisor for complex physical implementation<\/li>\n<\/ul>\n<p><strong>2015 - PULP-III<\/strong><br \/>\nFlexible multi-core platform for energy e\ufb03cient computing<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Participant in large, multi-partner project with ST-Microelectronics, UNIBO, ETH-Zurich, and CEA-Leti.<\/li>\n<li>Participant in architecture design and planning of body-bias generation block.<\/li>\n<\/ul>\n<p><strong>2015 - dynOR<\/strong><br \/>\nScalable CPU with early-edge detection and clock generation unit<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Project leader and head engineer.<\/li>\n<\/ul>\n<p><strong>2014 - CAMEL<\/strong><br \/>\nMemory and cryptography test chip<\/p>\n<ul>\n<li>Techonology: TSMC 65nm LP<\/li>\n<li>Advisor for design and physical implementation of multi-project test chip with Bar-Ilan University.<\/li>\n<\/ul>\n<p><strong>2014 - DDFSE<\/strong><br \/>\n60GHz wi-\ufb01 test chip<\/p>\n<ul>\n<li>Technology: TSMC 40nm LP<\/li>\n<li>Advisor for physical implementation of 2 Million gate, very complex hard macro.<\/li>\n<\/ul>\n<p><strong>2014 - PULP-II<\/strong><br \/>\nFlexible multi-core platform for energy e\ufb03cient computing<\/p>\n<ul>\n<li>Technology: ST 28nm FD-SOI<\/li>\n<li>Participant in large, multi-partner project with ST-Microelectronics, UNIBO, and ETH-Zurich.<\/li>\n<li>In charge of Standard Cell Memory block design and integration and special cell characterization and integration.<\/li>\n<\/ul>\n<p><strong>2013 - GREENBELT2<\/strong><br \/>\nGain-cell embedded DRAM and SRAM for space applications test chip<\/p>\n<ul>\n<li>Technology: UMC 0.18\u00b5m<\/li>\n<li>Led project, designed all included components, and carried out tape-out procedure, in collaboration with EPFL.<\/li>\n<\/ul>\n<p><strong>2012 - GREENBELT<\/strong><br \/>\nGain-cell embedded DRAM test chip2010\u20132012<\/p>\n<ul>\n<li>Technology: UMC 0.18\u00b5m<\/li>\n<li>Led project, designed all included components, and carried out tape-out procedure, in collaboration with EPFL.<\/li>\n<\/ul>\n<p><strong>2010\u20132012 - RFID<\/strong><br \/>\nSingle Chip RFID Demonstrator in standard CMOS process<\/p>\n<ul>\n<li>Technology: TowerJazz 0.18\u00b5m<\/li>\n<li>Participated in the design, tape-out procedures and measurements of 10 test-chips, as part of a multi-year project.<\/li>\n<li>Project culminated with a fully operational low-cost low-power RFID Demonstrator.<\/li>\n<li>Cooperation with Tel Aviv University and Tower Semiconductor.<\/li>\n<\/ul>\n<p><strong>2010 - RAMBO<\/strong><br \/>\nSubthreshold SRAM test chip.<\/p>\n<ul>\n<li>Technology: TSMC 40nm LP<\/li>\n<li>Led project, designed all included components, carried out tape-out procedure and measurements.<\/li>\n<li>First 40 nm test chip by an academic group in Israel.<\/li>\n<li>Cooperation with Zoran in tape-out procedure.<\/li>\n<\/ul>\n<p><strong>2008 - Sub-Vt<\/strong><br \/>\nSubthreshold logic test chip including AB2C smart imager<\/p>\n<ul>\n<li>Technology: TSMC 80nm<\/li>\n<li>Responsible for several of the included test circuits and components.<\/li>\n<li>Led full-chip integration and tape-out. Participated in measurements.<\/li>\n<li>Cooperation with Zoran in tape-out procedure.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>2019 &#8211;\u00a0SoC2 System-on-Chip Technology: TSMC 16FFC Co-academic director and leader of GC-eDRAM block 2018 &#8211;\u00a0Kwak Gain Cell eDRAM Test Chip and more Technology: Samsung 28nm FD-SOI Project Manager 2017 &#8211;\u00a0Martini Gain Cell eDRAM Test Chip and more Technology: ST 28nm FD-SOI Project Manager 2016 &#8211;\u00a0BEER Gain Cell eDRAM Test Chip and more Technology: ST 28nm &hellip; <a href=\"https:\/\/www.eng.biu.ac.il\/temanad\/research-tapeouts\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Research Tapeouts<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-51","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/51"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/comments?post=51"}],"version-history":[{"count":6,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/51\/revisions"}],"predecessor-version":[{"id":281,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/51\/revisions\/281"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/media?parent=51"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}