{"id":478,"date":"2020-06-09T11:52:18","date_gmt":"2020-06-09T08:52:18","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/temanad\/?page_id=478"},"modified":"2021-08-03T13:17:40","modified_gmt":"2021-08-03T10:17:40","slug":"conferences","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/temanad\/conferences\/","title":{"rendered":"Conferences"},"content":{"rendered":"

Peer-reviewed Conference Proceedings:<\/strong><\/h4>\n
    \n
  1. E. Garzon, R. De Rosea, F. Crupia, L. Trojmanc, A. Teman<\/strong> and M. Lanuzza, \"Relaxing Non-Volatility for Energy-Efficient DMTJ Based Cryogenic STT-MRAM\",<\/strong> in Insulating Films on Semiconductors (INFOS), pp. 2021<\/em><\/li>\n
  2. A. Avnon, R. Golman, E. Garzon, H.-D. Ngo, M. Lanuzza and A. Teman<\/strong>, \"Quantum Capacitance Transient Phenomena in High-K dielectric Armchair Graphene Nanoribbon Field-Effect Transistor Model\"<\/strong>, in Insulating Films on Semiconductors<\/em> (INFOS), pp., 2021<\/em><\/li>\n
  3. E. Levy, A. Sfez, R. Golman, O. Harel and A. Teman<\/strong>, \"4T Gain-Cell Providing Unlimited Availability Through Hidden Refresh with 1W1R Functionality\",<\/strong> in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), pp, May 2021<\/em><\/li>\n
  4. Y. Kra, T. Noy and A. Teman<\/strong>, \"WavePro 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining\"<\/strong> in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), DATE 2021, pp. ,2021<\/em><\/li>\n
  5. Y. Kra, T. Noy and A. Teman<\/strong>, \"WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation<\/a>,<\/strong>\"\u00a02020 Design, Automation & Test in Europe Conference & Exhibition (DATE)<\/em>, 2020, pp. 1291-1294<\/li>\n
  6. RR. Golman, R. Giterman, O. Harel and A. Teman<\/strong>, \"Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique<\/strong><\/a>,\"\u00a02020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, 2020, pp. 1-5<\/li>\n
  7. A. Bonetti, R. Golman, R. Giterman, A. Teman<\/strong> and A. Burg, \"Gain-Cell Embedded DRAMs: Modeling and Design Space<\/a>\"<\/strong> in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS)<\/em>, May 2020<\/li>\n
  8. R. Giterman, A. Bonetti, A. Burg and A. Teman<\/strong>, \"GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI<\/strong><\/a>,<\/strong><\/a>\" in\u00a0IEEE Transactions on Circuits and Systems (ISCAS) II: Express Briefs<\/em>, vol. 66, no. 12, pp. 2042-2046, Dec. 2019<\/li>\n
  9. A. Shalom, A. Fish and A. Teman<\/strong>, \"A 9pW\/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI<\/strong><\/a>,\"\u00a02019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, 2019, pp. 1-2<\/li>\n
  10. T. Munk, H. Kugler, O. Maori and A. Teman<\/strong>, \"TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches<\/strong><\/a>,\"\u00a02019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)<\/em>,pp. 1-4, Hsinchu, Taiwan, 2019<\/li>\n
  11. O. Maltabashi, H. Marinberg, R. Giterman and A. Teman<\/strong>, \"A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing<\/strong>,<\/a>\"\u00a02018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-5, Florence, 2018<\/li>\n
  12. A. Bonetti, J. Constantin, A. Teman<\/strong> and A. Burg, \"A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI<\/strong>,<\/a>\"\u00a02018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-4, Florence, 2018<\/li>\n
  13. R. Giterman, A. Fish, A. Burg and A. Teman<\/strong>, \"A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI<\/strong><\/a>,\" in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018.<\/em><\/li>\n
  14. A. Bonetti, A. Teman<\/strong>, P. Flatresse and A. Burg, \"Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters<\/strong><\/a>,<\/a>\" in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018<\/em><\/li>\n
  15. R. Golman, R. Giterman and A. Teman<\/strong>, \"A Dual-Negative Word-Line Technique for Improving Read Access in GC-eDRAM Arrays,\"<\/strong> in Proc. of the IEEE Int. Conf. on the Science of Electrical Engineering (ICSEE)<\/em>, December 2018<\/li>\n
  16. A. Shalom, R. Giterman and A. Teman<\/strong>, \"High Density GC-eDRAM Design in 16nm FinFET,\"<\/strong>\u00a02018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)<\/em>, pp. 585-588, Bordeaux, December 2018<\/li>\n
  17. R. Golman, R. Giterman and A. Teman<\/strong>, \"Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism,\"\u00a0<\/strong>2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)<\/em>, pp. 589-592, Bordeaux, December 2018<\/li>\n
  18. R. Giterman, A. Teman<\/strong> and A. Fish, \"A 14.3pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI,\"<\/strong>\u00a02018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2 Burlingame, CA, USA, Oct. 2018<\/li>\n
  19. R. Giterman, R. Golman, A. Shalom, O. Maltabashi, A. Fish and A. Teman<\/strong>, \"Live Demonstration<\/strong>: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications,\"\u00a0<\/strong>2018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-1, Florence, May 2018<\/li>\n
  20. R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman<\/strong>, \"An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications<\/strong><\/a>,\" ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference<\/em>, pp. 308-311,\u00a0 Leuven, Sept. 2017<\/li>\n
  21. R. Giterman, A. Teman<\/strong> and A. Fish, \"A 11.5pW\/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI<\/strong>,<\/a>\"\u00a02017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-3, San Francisco, CA, 2017<\/li>\n
  22. R. Giterman, A. Teman <\/strong>and P. Meinerzhagen, \u201c<\/strong>Highly Configurable Hybrid GC-eDRAM\/SRAM Bitcell for Robust Low-Power Operation<\/a>,<\/strong>\u201d<\/strong> in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS)<\/em>, 2017<\/li>\n
  23. J. Constantin, A. Bonetti, A. Teman<\/strong>, C. Mueller, L. Schmid, and A. Burg, \u201cDynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment<\/strong><\/a>,<\/a>\u201din \u00a0ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference<\/em>, pp. 261-264, Lausanne, September 2016<\/li>\n
  24. D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak, A. Teman<\/strong>, et al.,\u00a0\u201c193 MOPS\/mW @ 162\u00a0MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-E\ufb03cient Parallel and Sequential Digital Processing<\/strong>,\u201d in\u00a0 <\/a>2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)<\/em>, pp. 1-3, Yokohama, April 2016<\/li>\n
  25. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, A. Burg, and A. Fish, \u201cA process compensated gain cell\u00a0embedded DRAM for ultra low power variation aware design<\/strong><\/a>,\u201d in\u00a0 2016 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1006-1009, Montreal, QC, 2016<\/li>\n
  26. R. Ghanaatian, P. Whatmough, J. Constantin, A. Teman<\/strong>\u00a0and A. Burg, \u201cA low-power correlator for wake-up receivers with algorithm pruning through early termination<\/strong><\/a>,\u201d in 2016 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 2667-2670,\u00a0 Montreal, QC, May 2016<\/li>\n
  27. R. Giterman, A. Teman<\/strong>, L. Atias, and A. Fish, \u201cA soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications<\/strong><\/a>,\u201d in Proc. of IEEE S3S<\/em> , pp. 1-2, October 2015<\/li>\n
  28. S. Ganapathy, G. Karakonstantis, A. Teman<\/strong>\u00a0and A. Burg, \u201cMitigating the impact of faults in unreliable\u00a0memories for error-resilient applications<\/strong><\/a>,\u201d in Proc. of the Design Automation Conference (DAC) DAC<\/em>, pp. 102:1-106:6, ACM, NY., USA,\u00a0 2015<\/li>\n
  29. S. Ganapathy, A. Teman<\/strong>, R. Giterman, A. P. Burg and G. Karakonstantis, \u201cApproximate computing with unreliable dynamic memories<\/strong><\/a>,<\/strong>\u201d in Proc. of Int. New Circuits And Systems Conference (NEWCAS)<\/em>, pp. 1-4, June 2015 Special session on Approximate Computing.<\/li>\n
  30. A. Bonetti, A. Teman<\/strong>, and A. P. Burg, \u201cAn overlap-contention free true-single-phase clock dual-edge-triggered \ufb02ip-\ufb02op<\/strong>,<\/a>\u201d in Proc. of IEEE Int. Symp. on Circuits and Systems<\/em> (ISCAS), 2015<\/li>\n
  31. A. Teman<\/strong>, G. Karakonstantis, R. Giterman, P. Meinerzhagen and A. Burg, \u201cEnergy versus data\u00a0integrity trade-o\ufb00s in embedded high-density logic compatible dynamic memories<\/strong>,<\/a>\u201d in Proc. of the Design Automation and Test in Europe Conference Exhibition (DATE)<\/em>, DATE 2015, pp. 489\u2013494, San Jose, CA, USA, 2015<\/li>\n
  32. A. Teman<\/strong>, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, \u201cControlled placement of standard cell\u00a0memory arrays for high density and low power in 28nm FD-SOI<\/strong>,<\/a>\u201d in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC)<\/em> , pp. 81\u201386, 2015<\/li>\n
  33. L. Atias, A. Teman<\/strong> and A. Fish, \"Single event upset mitigation in low power SRAM design,\"<\/strong>\u00a02014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI)<\/em>, pp. 1-5, Eilat, 2014<\/li>\n
  34. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, A. Burg and A. Fish, \u201c4T gain-cell with internal-feedback\u00a0for ultra-low retention power at scaled CMOS nodes<\/strong><\/a>,<\/strong>\u201din 2014 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 2177-2180, Melbourne VIC, 2014<\/li>\n
  35. A. Teman<\/strong>, \u201cDynamic Stability and Noise Margins of SRAM Arrays in Nanoscaled Technologies<\/strong>,<\/a>\u201d in IEEE FTFC 2014<\/em>, pp. 1-5, Monte Carlo, Monaco<\/li>\n
  36. A. Vaknin, O. Yona and A. Teman<\/strong>, \"A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation,<\/a>\"<\/strong>\u00a02013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2, Monterey, CA, 2013<\/li>\n
  37. L. Atias, A. Teman<\/strong> and A. Fish, \"A 13T radiation hardened SRAM bitcell for low-voltage operation<\/a>,<\/a>\"<\/strong>\u00a02013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2, Monterey, CA, 2013<\/li>\n
  38. N. Edri, S. Fraiman, A. Teman<\/strong> and A. Fish, \"Data retention voltage detection for minimizing the standby power of SRAM arrays<\/a>,\"<\/strong>\u00a02012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 1-5, Eilat, 2012<\/li>\n
  39. A. Teman<\/strong>, P. Meinerzhagen, A. Burg and A. Fish, \"Review and classification of gain cell eDRAM implementations,<\/a>\"<\/strong>\u00a02012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 1-5, Eilat, 2012<\/li>\n
  40. P. Meinerzhagen, A. Teman<\/strong>, A. Mordakhay, A. Burg and A. Fish, \"A sub-VT 2T gain-cell memory for biomedical applications,<\/a>\"<\/strong>\u00a02012 IEEE Subthreshold Microelectronics Conference (SubVT)<\/em>, pp. 1-3, Waltham, MA, 2012<\/li>\n
  41. H. Dagan, A. Teman<\/strong>, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, \"A low-cost low-power non-volatile memory for RFID applications,<\/a>\"<\/strong>\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1827-1830, Seoul, 2012<\/li>\n
  42. H. Dagan, A. Teman<\/strong>, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, \"A GIDL free tunneling gate driver for a low power non-volatile memory array,<\/a>\"<\/strong>\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 452-455, Seoul, 2012<\/li>\n
  43. J. Mezhibovsky, A. Teman<\/strong> and A. Fish, \"State space modeling for sub-threshold SRAM stability analysis<\/a>,<\/a>\"<\/strong>\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1823-1826, Seoul, 2012<\/li>\n
  44. I. Schwartz, A. Teman<\/strong>, R. Dobkin and A. Fish, \"Near-threshold 40nm Supply Feedback C-element<\/a>,\"<\/strong>\u00a02011 3rd Asia Symposium on Quality Electronic Design (ASQED)<\/em>, pp. 74-78, Kuala Lumpur, 2011<\/li>\n
  45. J. Mezhibovsky, A. Teman<\/strong> and A. Fish, \"Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM,<\/a>\"<\/strong>\u00a02011 IEEE International SOC Conference<\/em>, pp. 136-141, Taipei, 2011<\/li>\n
  46. A. Teman<\/strong> and A. Fish, \"Sub-threshold and near-threshold SRAM design<\/a>,\"<\/strong>\u00a02010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 000608-000612, Eilat, 2010<\/li>\n
  47. A. Teman<\/strong>, O. Yadid-Pecht and A. Fish, \"An Improved AB2C scheme for leakage power reduction in image sensors with on-chip memory<\/a>,\"<\/strong>\u00a0SENSORS, 2009 IEEE<\/em>, pp. 193-196, Christchurch, 2009<\/li>\n
  48. S. Fisher, A. Teman<\/strong>, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, \"Ultra-low power subthreshold flip-flop design<\/a>,\"<\/strong>\u00a02009 IEEE International Symposium on Circuits and Systems<\/em>, pp. 1573-1576, Taipei, 2009<\/li>\n
  49. S. Fisher, A. Teman<\/strong>, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, \"Digital subthreshold logic design - motivation and challenges,<\/a>\"<\/strong>\u00a02008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 702-706 , Eilat, 2008<\/li>\n
  50. A. Teman,<\/strong> S. Fisher, L. Sudakov, A. Fish and O. Yadid-Pecht, \"Autonomous CMOS image sensor for real time target detection and tracking<\/a>,<\/strong>\"\u00a02008 IEEE International Symposium on Circuits and Systems<\/em>, pp. 2138-2141, Seattle, WA, 2008<\/li>\n<\/ol>\n

    Select Talks<\/strong><\/h4>\n
      \n
    1. O.\u00a0Maltabashi and A. Teman<\/strong>,\u00a0\"Controlled Placement of Standard Cell Memories with Innovus Implementation System<\/strong><\/a>\", in CDNLive Israel<\/em>, October 2017<\/li>\n
    2. A. Teman<\/strong>,\u00a0\"FD-SOI Standard Cell Characterization with Cadence Liberate<\/strong><\/a>\", in CDNLive Israel<\/em>, October 2016<\/li>\n
    3. A. Bonetti, N. Preyss, A. Burg, and A. Teman<\/strong>, \u201cDual-edge triggered clocking - how we can use it and when<\/strong><\/a>,\u201d in CDNLive Israel<\/em>, October 2015<\/li>\n
    4. A. Bonetti, N. Preyss, A. Teman<\/strong> and A. Burg, \u201cAutomated Integration of Dual-Edge Triggered Clocking Into the Standard Design Flow<\/strong><\/a>\u00a0,\u201d in CDNLive EDMA<\/em>, April 2015<\/li>\n
    5. A. Bonetti, J. Constantin, A. Teman<\/strong> and A. Burg, \u201cCircuits and techniques for dynamic timing monitoring in microprocessors<\/strong>,\u201d in Nanotera Annual Meeting 2015<\/em>, May 2015<\/li>\n
    6. A. Teman<\/strong>, G. Karakonstatis, S. Ganapathy, and A. Burg, \u201cExploiting application error resilience for energy savings in memories<\/em><\/strong>,\u201d in Workshop on Approximate Computing (WAPCO)<\/em>, January 2015<\/li>\n
    7. A. Teman<\/strong> and A. Fish, \u201cSRAM stability in the nanoscale era<\/em><\/strong>,\u201d in CDNLive Israel<\/em>, September 2012<\/li>\n
    8. A. Teman<\/strong> and A. Fish, \u201cLow voltage logic and SRAM design<\/em><\/strong><\/a>,\u201d in ChipEx 2011<\/em>, May 2011<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

      Peer-reviewed Conference Proceedings: E. Garzon, R. De Rosea, F. Crupia, L. Trojmanc, A. Teman and M. Lanuzza, “Relaxing Non-Volatility for Energy-Efficient DMTJ Based Cryogenic STT-MRAM”, in Insulating Films on Semiconductors (INFOS), pp. 2021 A. Avnon, R. Golman, E. Garzon, H.-D. Ngo, M. Lanuzza and A. Teman, “Quantum Capacitance Transient Phenomena in High-K dielectric Armchair Graphene … Continue reading Conferences<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":76,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-478","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/478"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/users\/76"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/comments?post=478"}],"version-history":[{"count":111,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/478\/revisions"}],"predecessor-version":[{"id":865,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/478\/revisions\/865"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/media?parent=478"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}