{"id":465,"date":"2020-06-09T11:04:07","date_gmt":"2020-06-09T08:04:07","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/temanad\/?page_id=465"},"modified":"2021-08-03T12:14:34","modified_gmt":"2021-08-03T09:14:34","slug":"journals","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/temanad\/journals\/","title":{"rendered":"Journals"},"content":{"rendered":"<h4 style=\"text-align: justify\"><strong>Journal Articles:<\/strong><\/h4>\n<ol>\n<li>E. Garzon, R. De Rose, F. Crupi, <strong>A. Teman<\/strong> and M. Lanuzza, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9316299\"><strong>Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications<\/strong><\/a>\", <em>IEEE Transactions on Nanotechnology<\/em>, vol. 20, pp. 123-128, 2021<\/li>\n<li>R. Giterman, A. Shalom, A. Burg, A. Fish and\u00a0 <strong>A. Teman<\/strong> - \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9131838\"><strong>A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET<\/strong>\"<\/a>, in <em>IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 110-113, 2020<\/li>\n<li>T. Noy and <strong>A. Teman<\/strong>, \"<a href=\"http:\/\/Design of a Refresh-Controller for GC-eDRAM Based FIFOs\" data-wplink-url-error=\"true\"><strong>Design of a Refresh-Controller for GC-eDRAM Based FIFOs<\/strong><\/a>\" in \u00a0<em>IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 67, no. 12, pp. 4804-4817, Dec. 2020<\/li>\n<li>A. Haran, E. Keren, D. David, N. Refaeli, R. Giterman, M. Assaf, L. Atias, <strong>A. Teman<\/strong> and A. Fish, \"<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/9117141\"><strong>Single Event Upset Tolerance Study of a Low Voltage 13T Radiation-Hardened SRAM Bitcell<\/strong><\/a><a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?tp=&amp;arnumber=9117141\">,<\/a>\" in <em>IEEE Transactions on Nuclear Science, <\/em>pp. 1-12<em>, <\/em>2020<\/li>\n<li>O. Harel, Y. Nachum and R. Giterman, \u201c<a href=\"https:\/\/www.sciencedirect.com\/science\/article\/abs\/pii\/S0026269219305932\"><strong>Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM<\/strong><\/a>\u201d in <em>Microelectronics Journal, <\/em>vol.\u00a0101, July 2020<\/li>\n<li>D. Vana, P.E. Gaillardon and <strong>A. Teman<\/strong>, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8959396\"><strong>C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors<\/strong><\/a><em>\", IEEE Transactions on Nanotechnology, <\/em>vol. 19, pp. 123-136<em>, <\/em>Jan. 2020<\/li>\n<li style=\"text-align: justify\">R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, <strong>A. Teman<\/strong> and A. Burg, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/9003520\"><strong>Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space<\/strong><\/a>,\" in\u00a0<em>IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 67, no. 4, pp. 1207-1217, April 2020<\/li>\n<li style=\"text-align: justify\">A. Bonetti, R. Golman, R. Giterman, <strong>A. Teman<\/strong> and A. Burg, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8951129\"><strong>Gain-Cell Embedded DRAMs: Modeling and Design Space<\/strong><\/a><em>\", <\/em>in<em> IEEE Transactions on Very Large Scale Integration (VLSI) Systems, <\/em>vol. 28, no. 3, pp. 646-659<em>, <\/em>March 2020<\/li>\n<li style=\"text-align: justify\">O. Maltabashi, Y. Kra and <strong>A. Teman<\/strong>, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8772144\"><strong>Physically-aware Affinity-driven Multiplier Implementation<\/strong><\/a><em>\", <\/em>in<em> IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, <\/em>pp. 1-1, 2019<\/li>\n<li style=\"text-align: justify\">R. Giterman, A. Bonetti, A. Burg and <strong>A. Teman<\/strong>, <em>\"<\/em><a href=\"https:\/\/ieeexplore.ieee.org\/document\/8630062\"><strong>GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI<\/strong><\/a><em>,\"<\/em> in <em>IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 66, no. 12, pp. 2042-2046, Dec. 2019<\/li>\n<li style=\"text-align: justify\">R. Giterman, R. Golman and <strong>A. Teman<\/strong>, \"<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8653811\"><strong>Improving energy-efficiency in dynamic memories through retention failure detection<\/strong><\/a><a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?tp=&amp;arnumber=8653811\">,<\/a>\" in <em>IEEE Access<\/em>, vol. 7, pp. 27641-27649, 2019<\/li>\n<li style=\"text-align: justify\">R. Giterman, Y. Weizman and <strong>A. Teman<\/strong>, <em>\"<\/em><a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8391755\"><strong>Gain-Cell Embedded DRAM Based Physical Unclonable Function<\/strong><\/a>,\" in<em> IEEE trans. Circuits Syst. I<\/em>, vol. 65, pp. 4208-4218, Dec 2018<\/li>\n<li style=\"text-align: justify\">R. Giterman, A. Fish, A. Burg and <strong>A. Teman<\/strong>, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8036208\"><strong>A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With over 1.6-ms Retention Time at 700 mV in\u00a0 28-nm FD-SOI<\/strong><\/a><strong>,<\/strong>\" in <em>IEEE Trans. Circuits Syst. I<\/em>, vol. 65, pp. 1245-1256, April 2018<\/li>\n<li style=\"text-align: justify\">R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and <strong>A. Teman<\/strong>, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/8356248\"><strong>An 800MHz Mixed-VT 4T IFGC Embedded DRAM in 28nm CMOS Bulk Process for Approximate Storage Applications<\/strong><\/a>\", in <em>IEEE J. Solid Circuits<\/em>, vol. 53, pp. 2136-2148, July 2018<\/li>\n<li style=\"text-align: justify\">R. Ghanaatian, A. Balatsoukas-Stimming, C. Muller, M. Meidlinger, G. Matz, <strong>A. Teman<\/strong>\u00a0and A. Burg, <em>\"<\/em><a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8113527\"><strong>A 588-Gb\/s LDPC Decoder Based on Finite-Alphabet Message Passing<\/strong>,<\/a>\" in <em>IEEE Trans<\/em>. <em>VLSI Syst<\/em>., vol. 26, pp. 329-340, Feb 2018<\/li>\n<li style=\"text-align: justify\">R. Giterman, <strong>A. Teman<\/strong> and P. Meinerzhagen, \"<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8089774\"><strong>Hybrid GC-eDRAM\/SRAM Bitcell for Robust Low-Power Operation<\/strong><\/a>\", in <em>IEEE trans. Circuits Syst. II, <\/em>vol. 64, pp. 1362-1366, Dec 2017<\/li>\n<li style=\"text-align: justify\">A. Bonetti, <strong>A. Teman<\/strong>, P. Flatresse and A. Burg, \"<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7927747\"><strong>Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters<\/strong><\/a>,\" in\u00a0<em>IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 64, no. 9, pp. 2388-2400, September 2017<\/li>\n<li style=\"text-align: justify\">A. Kazimirsky, <strong>A. Teman<\/strong>, N. Edri and\u00a0 A. Fish, <strong>\"<\/strong><a href=\"https:\/\/ieeexplore.ieee.org\/document\/7956276\"><strong>An 0.65V 500MHz Integrated Dynamic and Static RAM (iD-SRAM) for Error Tolerant Applications<\/strong><\/a><strong>\"<\/strong> in<em> IEEE trans. Circuits Syst. , <\/em>vol. 25, no. 9, pp. 2411-2418, September 2017<\/li>\n<li style=\"text-align: justify\">D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Kagan Gurkaynak, <strong>A. Teman<\/strong>, et al.,\u00a0<strong>\u201c<\/strong><a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/8065010\"><strong>Energy Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster<\/strong><\/a><strong>,\u201d<\/strong>\u00a0 in <em>IEEE Micro<\/em>, vol. 37, pp. 20-31, September 2017<\/li>\n<li style=\"text-align: justify\">A. Bonetti, N. Preyss, <strong>A. Teman <\/strong>and A. Burg, <strong>\u201c<\/strong><a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3054744\"><strong>Automated Integration of Dual-Edge Clocking for Low-Power\u00a0Operation in Nanometer Nodes<\/strong><\/a><strong>,\u201d <\/strong>in <em>ACM Trans. on Design Automation of Elec. Systems<\/em>, vol. 22, pp. 62:1-62:20, May 2017<\/li>\n<li style=\"text-align: justify\">R. Giterman, L. Atias and <strong>A. Teman<\/strong>, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/abstract\/document\/7563385\"><strong>Area and energy-e\ufb03cient complementary dual-modular redundancy dynamic memory for space applications<\/strong><\/a>,\u201d\u00a0 in <em>IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/em>, vol. 25, no. 2, pp. 502-509, Feb. 2017<\/li>\n<li style=\"text-align: justify\">L. Moyal, I. Levi, <strong>A. Teman<\/strong>\u00a0and A. Fish, \u201c<a href=\"https:\/\/www.sciencedirect.com\/science\/article\/abs\/pii\/S0167926016300360\"><strong>Synthesis of dual mode logic<\/strong>,<\/a>\u201d in <em>Integration - The VLSI Journal (VLSI-D)<\/em>, vol. 55, pp. 246\u2013253, 2016<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, D. Rossi, P. Meinerzhagen, L. Benini and A. Burg, \u201c<a href=\"http:\/\/delivery.acm.org\/10.1145\/2900000\/2890498\/a59-teman.pdf?ip=132.70.227.129&amp;id=2890498&amp;acc=ACTIVE%20SERVICE&amp;key=0D17F1A88EABC760%2EE8BDD9D808F7A2BA%2E4D4702B0C3E38B35%2E4D4702B0C3E38B35&amp;__acm__=1566285319_6cc020007d9b28ac096644451cb8dd54\"><strong>Power, area, and performance optimization of standard cell memory arrays through controlled placement<\/strong><\/a>,\u201d in <em>ACM TODAES<\/em>, vol. 21, pp. 59:1\u201359:25, May 2016<\/li>\n<li style=\"text-align: justify\">L. Atias, <strong>A. Teman<\/strong>, R. Giterman, P. Meinerzhagen and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7404051\"><strong>A low-voltage 13T radiation hardened\u00a0SRAM bitcell for low-voltage operation<\/strong>,<\/a>\u201d in <em>IEEETVLSI<\/em>, vol. 24, no. 8, pp. 2622\u20132633, 2016<\/li>\n<li style=\"text-align: justify\">N. Edri, P. Meinerzhagen, <strong>A. Teman<\/strong>, A. Burg and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7430275\"><strong>Silicon-proven per-cell retention time\u00a0distribution model of gain-cell based eDRAM<\/strong><\/a>,\u201d in <em>IEEE TCAS-I<\/em>, vol. 63, pp. 222\u2013232, Feb 2016<\/li>\n<li style=\"text-align: justify\">R. Giterman, <strong>A. Teman<\/strong>, P. Meinerzhagen, L. Atias, A. Burg and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/7031447?arnumber=7031447\"><strong>Single-supply 3T gain-cell\u00a0for low-voltage low-power applications<\/strong>,<\/a>\u201d in <em>IEEE TVLSI<\/em>, vol. 24, no. 1, pp. 358\u2013362, 2016<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong> and R. Visotsky, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6923443\"><strong>A fast modular method for true variation-aware separatrix tracing in\u00a0nanoscaled SRAMs<\/strong><\/a>,\u201d in <em>IEEE TVLSI<\/em>, vol. 23, no. 10, pp. 2034\u20132042, 2015<\/li>\n<li style=\"text-align: justify\">H. Dagan, A. Shapira, <strong>A. Teman<\/strong>, A. Mordakhay, S. Jameson, E. Pikhay, V. Dayan, Y. Roizin, E. Socher,\u00a0and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6832604\"><strong>A low-power low-cost 24 GHz RFID tag with a C-Flash based embedded memory<\/strong>,<\/a>\u201d in\u00a0 <em>IEEE\u00a0JSSC<\/em>, vol. 49, no. 9, pp. 1942\u20131957, 2014<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, P. Meinerzhagen, R. Giterman, A. Fish, and A. Burg, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6754136\"><strong>Replica technique for adaptive refresh timing of gain-cell-embedded DRAM<\/strong><\/a><a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?tp=&amp;arnumber=6754136\">,<\/a>\u201d in <em>IEEE TCAS-II<\/em>, vol. 61, no. 4, pp. 259\u2013263, 2014<\/li>\n<li style=\"text-align: justify\">P. Meinerzhagen, <strong>A. Teman<\/strong>, A. Fish and A. Burg, \"<a href=\"https:\/\/ieeexplore.ieee.org\/stamp\/stamp.jsp?tp=&amp;arnumber=8410960\"><strong>Impact of body biasing on the retention time of gain-cell memories<\/strong><\/a><strong>,<\/strong>\" in <em>The Journal Of Engineering<\/em>, vol. 1, no. 1, 2013<\/li>\n<li style=\"text-align: justify\">P. Meinerzhagen, <strong>A. Teman<\/strong>, R. Giterman, A. Burg and A. Fish, \u201c<a href=\"https:\/\/www.mdpi.com\/2079-9268\/3\/2\/54\/htm\"><strong>Exploration of sub-VT and near-VT\u00a02T gain-cell memories for ultra-low power applications under technology scaling<\/strong><\/a>,\u201d in <em>MDPI JLPEA<\/em>, vol. 3, no. 2, pp. 54\u201372, 2013<\/li>\n<li style=\"text-align: justify\">H. Dagan, <strong>A. Teman<\/strong>, E. Pikhay, V. Dayan, A. Mordakhay, Y. Roizin and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6492123\"><strong>A low-power\u00a0DCVSL-like GIDL-free voltage driver for low-cost RFID nonvolatile memory<\/strong>,<\/a>\u201d <em>IEEE JSSC<\/em>, vol. 4, no. 6, pp. 1497\u20131510, 2013<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, A. Mordakhay, and A. Fish, \u201c<a href=\"https:\/\/reader.elsevier.com\/reader\/sd\/pii\/S002626921200256X?token=78B04F6E6A3733C3766D8DAC5EE29AAA84D8E9816B9DD1ECFD407B215381A728BB7C24D53BC3C58507CC2095541219F7\"><strong>Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell<\/strong>,<\/a>\u201d in <em>Microelectronics Journal<\/em>, vol. 44, no. 3, pp. 236\u2013247, 2013<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, H. Dagan, V. Dayan, E. Pikhay, Y. Roizin, and A. Fish, \"<strong>Zero-cost ultra-low power non-volatile memory module for RFID applications<\/strong>,\" <em>Tower Jazz Technical Journal<\/em>, vol. 4, pp. 46-49, July 2013<\/li>\n<li style=\"text-align: justify\">A. Spivak, <strong>A. Teman<\/strong>, A. Belenky, O. Yadid-Pecht and A. Fish, \u201c<a href=\"https:\/\/www.researchgate.net\/publication\/261267929_A_low-cost_low-power_non-volatile_memory_for_RFID_applications\"><strong>Low-voltage 96 dB snapshot CMOS\u00a0image sensor with 4.5 nW power dissipation per pixel<\/strong><\/a>,\u201d in <em>MDPI Sensors<\/em>, vol. 12, no. 8, pp. 10067\u201310085, 2012<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, O. Yadid-Pecht and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/5771526\"><strong>Leakage reduction in advanced image sensors using an\u00a0improved AB2C scheme<\/strong>,<\/a>\u201d in <em>IEEE Sensors Journal<\/em>, vol. 12, no. 4, pp. 773\u2013784, 2012<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, A. Mordakhay, J. Mezhibovsky and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6407964\"><strong>A 40-nm sub-threshold 5T SRAM bit cell\u00a0with improved read and write stability<\/strong>,<\/a>\u201d in <em>IEEE TCAS-II<\/em>, vol. 59, no. 12, pp. 873\u2013877, 2012<\/li>\n<li style=\"text-align: justify\">A. Spivak, <strong>A. Teman<\/strong>, A. Belenky, O. Yadid-Pecht and A. Fish, \"<a href=\"https:\/\/www.mdpi.com\/2079-9268\/1\/1\/59\"><strong>Power-performance tradeoffs in wide dynamic range image sensors with multiple reset approach<\/strong><\/a><strong>,<\/strong>\" in <em>MDPI J. Low Power Elec. and App<\/em>., vol. 1, no. 1, pp. 59-76, 2011<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, L. Pergament, O. Cohen and A. Fish, \"<a href=\"https:\/\/www.researchgate.net\/publication\/228872778_A_minimum_leakage_quasi-static_RAM_bitcell\"><strong>A minimum leakage quasi-static RAM bitcell<\/strong><\/a><strong>,<\/strong>\" in <em>MDPI J. Low Power Elec. and App<\/em>., vol.1, no. 1, pp. 204-218, 2011<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, L. Pergament, O. Cohen and A. Fish, \u201c<a href=\"https:\/\/ieeexplore.ieee.org\/document\/6008514\"><strong>A 250 mV 8 kb 40 nm ultra-low power 9T supply\u00a0feedback SRAM (SF-SRAM)<\/strong>,<\/a>\u201d in <em>IEEE JSSC<\/em>, vol. 46, no. 11, pp. 2713\u20132726, 2011<\/li>\n<li style=\"text-align: justify\"><strong>A. Teman<\/strong>, O. Yadid-Pecht, and A. Fish, \"<a href=\"http:\/\/citeseerx.ist.psu.edu\/viewdoc\/download?doi=10.1.1.386.8830&amp;rep=rep1&amp;type=pdf#page=102\"><strong>Large VLSI arrays - power and architectural perspectives<\/strong><\/a>\"<em> International Journal of Information Technologies and Knowledge (IJ ITK), vol. 4, no. 1, pp. 76-90, 2010<\/em><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p>Journal Articles: E. Garzon, R. De Rose, F. Crupi, A. Teman and M. Lanuzza, &#8220;Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications&#8221;, IEEE Transactions on Nanotechnology, vol. 20, pp. 123-128, 2021 R. Giterman, A. Shalom, A. Burg, A. Fish and\u00a0 A. Teman &#8211; &#8220;A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET&#8221;, in IEEE &hellip; <a href=\"https:\/\/www.eng.biu.ac.il\/temanad\/journals\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Journals<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":76,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-465","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/465"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/users\/76"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/comments?post=465"}],"version-history":[{"count":129,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/465\/revisions"}],"predecessor-version":[{"id":793,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/465\/revisions\/793"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/media?parent=465"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}