{"id":26,"date":"2015-10-28T11:41:56","date_gmt":"2015-10-28T09:41:56","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/temanad\/?page_id=26"},"modified":"2020-06-09T06:38:09","modified_gmt":"2020-06-09T03:38:09","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/temanad\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"

Books and Book Chapters:<\/h4>\n
    \n
  1. P. Meinerzhagen, A. Teman, R. Giterman, N. Edri, A. Burg and A. Fish<\/strong> - \u201cGain-Cell Embedded DRAMs for Low Power VLSI Systems-on-Chip\u201d,\u00a0 Springer International Publishing, 2018.<\/li>\n<\/ol>\n

    Journal Articles:<\/h4>\n
      \n
    1. R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, A. Teman and A. Burg, \"Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space,\" in\u00a0IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 67, no. 4, pp. 1207-1217, April 2020<\/li>\n
    2. D. Vana, p.E. Gaillardon and A.Teman<\/strong>, \"C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors<\/a><\/strong>\", IEEE Transactions on Nanotechnology, vol. 19, pp. 123-136, <\/em>Jan. 2020<\/li>\n
    3. A. Bonetti, R. Golman, R. Giterman, A. Teman<\/strong> and A. Burg, \"Gain-Cell Embedded DRAMs: Modeling and Design Space<\/a><\/strong>\", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 646-659, <\/em>March 2020<\/li>\n
    4. O. Maltabashi, Y. Kra and A. Teman<\/strong>, \"Physically-aware Affinity-driven Multiplier Implementation<\/a><\/strong>\", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, <\/em>2019<\/li>\n
    5. R. Giterman, A. Bonetti, A. Burg, A. Teman<\/strong>, \"GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI<\/strong><\/a>,\"<\/em> IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 66, no. 12, pp. 2042-2046, Dec. 2019<\/li>\n
    6. R. Giterman, R. Golman, and A. Teman<\/strong>, \"Improving energy-efficiency in dynamic memories through retention failure detection<\/strong>,<\/a>\"<\/em> \u00a0IEEE Access<\/em>, vol. 7, pp. 27641-27649, 2019<\/li>\n
    7. R. Giterman, Y. Weizman, and A. Teman<\/strong>, \"Gain-Cell Embedded DRAM Based Physical Unclonable Function<\/strong><\/a>,\" IEEE trans. Circuits Syst. I<\/em>, vol. 65, pp. 4208-4218, Dec 2018.<\/li>\n
    8. R. Giterman, A. Fish, A. Burg, and A. Teman<\/strong>, \"<\/em>A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With over 1.6-ms Retention Time at 700 mV in\u00a0 28-nm FD-SOI<\/em><\/a>,<\/strong>\" IEEE Trans. Circuits Syst. I<\/em>, vol. 65, pp. 1245-1256, April 2018.<\/li>\n
    9. R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg, and A. Teman<\/strong>, \"An 800MHz Mixed-VT 4T IFGC Embedded DRAM in 28nm CMOS Bulk Process for Approximate Storage Applications<\/strong><\/a>\"<\/em>, IEEE J. Solid Circuits<\/em>, vol. 53, pp. 2136-2148, July 2018.<\/li>\n
    10. R. Ghanaatian, A. Balatsoukas-Stimming, C. Muller, M. Meidlinger, G. Matz, A. Teman<\/strong>, and A. Burg, \"A 588-Gb\/s LDPC Decoder Based on Finite-Alphabet Message Passing<\/strong><\/a>,\"<\/em> IEEE Trans<\/em>. VLSI Syst<\/em>., vol. 26, pp. 329-340, Feb 2018.<\/li>\n
    11. R. Giterman, A. Teman<\/strong> and P. Meinerzhagen, \"Hybrid GC-eDRAM\/SRAM Bitcell for Robust Low-Power Operation<\/a><\/strong><\/em>\", IEEE trans. Circuits Syst. II, vol. 64, pp. 1362-1366, Dec 2017.<\/em><\/li>\n
    12. A. Kazimirsky, A. Teman<\/strong>, N. Edri, A. Fish \"An 0.65V 500MHz Integrated Dynamic and Static RAM (iD-SRAM) for Error Tolerant Applications<\/a>\"<\/strong> IEEE trans. Circuits Syst. , vol. 25, no. 9, pp. 2411-2418, Sep. 2017.<\/em><\/li>\n
    13. A. Bonetti, A. Teman<\/strong>, P. Flatresse, A. Burg, \"Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters<\/a>\"<\/em><\/strong> Accepted to IEEE TCAS-I, 2017.<\/li>\n
    14. A. Bonetti, N. Preyss, A. Teman<\/strong>, A. Burg, \u201cAutomated Integration of Dual-Edge Clocking for Low-Power\u00a0Operation in Nanometer Nodes<\/a>,\u201d <\/strong><\/em>Accepted to ACM TODAES, 2017.<\/li>\n
    15. D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak, A. Teman<\/strong>, et al.,\u00a0\u201cEnergy Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster<\/a>,\u201d<\/em><\/strong> Accepted to IEEE Micro, 2017.<\/li>\n
    16. R. Giterman, L. Atias, and A. Teman<\/strong>, \u201cArea and energy-e\ufb03cient complementary dual-modular redundancy dynamic memory for space applications<\/em><\/strong><\/a>,\u201d IEEE TVLSI, vol. PP, no. 99, pp. 1\u20138, 2016<\/li>\n
    17. L. Moyal, I. Levi, A. Teman<\/strong>, and A. Fish, \u201cSynthesis of dual mode logic<\/em><\/strong><\/a>,\u201d Integration the VLSI Journal (VLSI-D),\u00a0vol. 55, pp. 246\u2013253, 2016<\/li>\n
    18. A. Teman<\/strong>, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, \u201cPower, area, and performance optimization of standard cell memory arrays through controlled placement<\/em><\/strong><\/a>,\u201d ACM TODAES, vol. 21, pp. 59:1\u201359:25, May 2016<\/li>\n
    19. L. Atias, A. Teman<\/strong>, R. Giterman, P. Meinerzhagen, and A. Fish, \u201cA low-voltage 13T radiation hardened\u00a0SRAM bitcell for low-voltage operation<\/em><\/strong>,<\/a>\u201d IEEETVLSI, vol. 24, no. 8, pp. 2622\u20132633, 2016<\/li>\n
    20. N. Edri, P. Meinerzhagen, A. Teman<\/strong>, A. Burg, and A. Fish, \u201cSilicon-proven per-cell retention time\u00a0distribution model of gain-cell based eDRAM<\/em><\/strong><\/a>,\u201d IEEE TCAS-I, vol. 63, pp. 222\u2013232, Feb\u00a02016<\/li>\n
    21. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, L. Atias, A. Burg, and A. Fish, \u201cSingle-supply 3T gain-cell\u00a0for low-voltage low-power applications<\/em><\/strong><\/a>,\u201d IEEE TVLSI<\/em>, vol. 24, no. 1, pp. 358\u2013362, 2016<\/li>\n
    22. A. Teman<\/strong> and R. Visotsky, \u201cA fast modular method for true variation-aware separatrix tracing in\u00a0nanoscaled SRAMs<\/em><\/strong><\/a>,\u201d IEEE TVLSI<\/em>, vol. 23, no. 10, pp. 2034\u20132042, 2015<\/li>\n
    23. H. Dagan, A. Shapira, A. Teman<\/strong>, A. Mordakhay, S. Jameson, E. Pikhay, V. Dayan, Y. Roizin, E. Socher,\u00a0and A. Fish, \u201cA low-power low-cost 24 GHz RFID tag with a C-Flash based embedded memory<\/em><\/strong>,<\/a>\u201d IEEE\u00a0JSSC<\/em>, vol. 49, no. 9, pp. 1942\u20131957, 2014<\/li>\n
    24. A. Teman<\/strong>, P. Meinerzhagen, R. Giterman, A. Fish, and A. Burg, \u201cReplica technique for adaptive refresh timing of gain-cell-embedded DRAM<\/em><\/strong>,<\/a>\u201d IEEE TCAS-II<\/em>, vol. 61, no. 4, pp. 259\u2013263, 2014<\/li>\n
    25. P. Meinerzhagen, A. Teman<\/strong>, A. Fish and A. Burg, \"Impact of body biasing on the retention time of gain-cell memories<\/a>,<\/strong>\"<\/em> The Journal Of Engineering<\/em>, vol. 1, no. 1, 2013<\/li>\n
    26. P. Meinerzhagen, A. Teman<\/strong>, R. Giterman, A. Burg, and A. Fish, \u201cExploration of sub-VT and near-VT\u00a02T gain-cell memories for ultra-low power applications under technology scaling<\/em><\/strong><\/a>,\u201d MDPI JLPEA, vol. 3, no. 2, pp. 54\u201372, 2013<\/li>\n
    27. H. Dagan, A. Teman<\/strong>, E. Pikhay, V. Dayan, A. Mordakhay, Y. Roizin, and A. Fish, \u201cA low-power\u00a0DCVSL-like GIDL-free voltage driver for low-cost RFID nonvolatile memory<\/em><\/strong><\/a>,\u201d IEEE JSSC<\/em>, vol. 4, no. 6, pp. 1497\u20131510, 2013<\/li>\n
    28. A. Teman<\/strong>, A. Mordakhay, and A. Fish, \u201cFunctionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell<\/em><\/strong>,<\/a>\u201d Microelectronics Journal, vol. 44, no. 3, pp. 236\u2013247, 2013<\/li>\n
    29. A. Teman<\/strong>, H. Dagan, V. dayan, E. Pikhay, Y. Roizin, and A. Fish, \"Zero-cost ultra-low power non-volatile memory module for RFID applications<\/strong>,\"<\/em> TowerJazz Technical Journal<\/em>, vol. 4, pp. 46-49, July 2013<\/li>\n
    30. A. Spivak, A. Teman<\/strong>, A. Belenky, O. Yadid-Pecht, and A. Fish, \u201cLow-voltage 96 dB snapshot CMOS\u00a0image sensor with 4.5 nW power dissipation per pixel<\/em><\/strong>,<\/a>\u201d MDPI Sensors, vol. 12, no. 8, pp. 10067\u201310085,\u00a02012<\/li>\n
    31. A. Teman<\/strong>, O. Yadid-Pecht, and A. Fish, \u201cLeakage reduction in advanced image sensors using an\u00a0improved AB2C scheme<\/em><\/strong><\/a>,\u201d IEEE Sensors Journal, vol. 12, no. 4, pp. 773\u2013784, 2012<\/li>\n
    32. A. Teman<\/strong>, A. Mordakhay, J. Mezhibovsky, and A. Fish, \u201cA 40-nm sub-threshold 5T SRAM bit cell\u00a0with improved read and write stability<\/em><\/strong>,<\/a>\u201d IEEE TCAS-II, vol. 59, no. 12, pp. 873\u2013877, 2012<\/li>\n
    33. A. Spivak, A. Teman<\/strong>, A. Belenky, O. Yadid-Pecht, and A. Fish, \"Power-performance tradeoffs in wide dynamic range image sensors with multiple reset approach<\/a>,<\/strong>\"<\/em> MDPI J. Low Power Elec. and App<\/em>., vol. 1, no. 1, pp. 59-76, 2011<\/li>\n
    34. A. Teman<\/strong>, L. Pergament, O. Cohen, and A. Fish, \"A minimum leakage quasi-static RAM bitcell<\/a><\/em>,<\/strong>\" MDPI J. Low Power Elec. and App<\/em>., vol.1, no. 1, pp. 204-218, 2011<\/li>\n
    35. A. Teman<\/strong>, L. Pergament, O. Cohen, and A. Fish, \u201cA 250 mV 8 kb 40 nm ultra-low power 9T supply\u00a0feedback SRAM (SF-SRAM)<\/em><\/strong>,<\/a>\u201d IEEE JSSC, vol. 46, no. 11, pp. 2713\u20132726, 2011<\/li>\n
    36. A. Teman<\/strong>, O. Yadid-Pecht, and A. Fish, \"Large VLSI arrays - power and architectural perspectives<\/a><\/strong>\" International Journal of Information Technologies and Knowledge (IJ ITK), vol. 4, no. 1, pp. 76-90, 2010<\/em><\/li>\n<\/ol>\n

      Peer-reviewed Conference Proceedings:<\/h4>\n
        \n
      1. Y. Kra, T. Noy and A. Teman<\/strong>, \"Wavepro: Clock-less wave-propagated pipeline compiler for low-power and high-throughput computation\" in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/em>, DATE 2020<\/li>\n
      2. A. Shalom, A. Fish and A. Teman<\/strong>, \"A 9pW\/bit 440mV 3T Gain-Cell eDRAM for ULP Applications in 28nm FD-SOI\" in Proc. of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, October 2019<\/li>\n
      3. T. Munk, H. Kugler, O. Maori and A. Teman<\/strong>, \"TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches,\"\u00a02019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)<\/em>,pp. 1-4, Hsinchu, Taiwan, 2019<\/li>\n
      4. O. Maltabashi, H. Marinberg, R. Giterman and A. Teman<\/strong>, \"A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing,\"\u00a02018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-5, Florence, 2018<\/li>\n
      5. A. Bonetti, J. Constantin, A. Teman<\/strong> and A. Burg, \"A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI,\"\u00a02018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-4, Florence, 2018<\/li>\n
      6. R. Giterman, A. Fish, A. Burg and A. Teman<\/strong>, \"A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI,\" in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018.<\/i><\/li>\n
      7. A. Bonetti, A. Teman<\/strong>, P. Flatresse and A. Burg, \"Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters,\" in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2018<\/i><\/li>\n
      8. R. Golman, R. Giterman and A. Teman<\/strong>, \"A Dual-Negative Word-Line Technique for Improving Read Access in GC-eDRAM Arrays,<\/strong>\" in Proc. of the IEEE Int. Conf. on the Science of Electrical Engineering (ICSEE)<\/em>, December 2018<\/li>\n
      9. A. Shalom, R. Giterman and A. Teman<\/strong>, \"High Density GC-eDRAM Design in 16nm FinFET,\"\u00a02018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)<\/em>, pp. 585-588, Bordeaux, December 2018<\/li>\n
      10. R. Golman, R. Giterman and A. Teman<\/strong>, \"Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism,\"\u00a02018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)<\/em>, pp. 589-592, Bordeaux, December 2018<\/li>\n
      11. R. Giterman, A. Teman<\/strong> and A. Fish, \"A 14.3pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI,\"\u00a02018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2 Burlingame, CA, USA, Oct. 2018<\/li>\n
      12. R. Giterman, R. Golman, A. Shalom, O. Maltabashi, A. Fish and A. Teman<\/strong>, \"Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications,\"\u00a02018 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1-1, Florence, May 2018<\/li>\n
      13. R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman<\/strong>, \"An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications,\" ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference<\/em>, pp. 308-311,\u00a0 Leuven, Sept. 2017<\/li>\n
      14. R. Giterman, A. Teman and A. Fish, \"A 11.5pW\/bit 400mV 5T gain-cell eDRAM for ULP applications in 28nm FD-SOI,\"\u00a02017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-3, San Francisco, CA, 2017<\/li>\n
      15. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, \u201cHighly Configurable Hybrid GC-eDRAM\/SRAM Bitcell for Robust Low-Power Operation,<\/a>\u201d<\/em><\/strong> in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS)<\/em>, 2017<\/li>\n
      16. J. Constantin, A. Bonetti, A. Teman<\/strong>, C. Mueller, L. Schmid, and A. Burg, \u201cDynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment<\/em><\/strong>,<\/a>\u201din \u00a0ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference<\/em>, pp. 261-264, Lausanne, September 2016<\/li>\n
      17. D. Rossi, A. Pullini, I. Loi, M. Gautschi, F. Gurkaynak, A. Teman<\/strong>, et al.,\u00a0\u201c193 MOPS\/mW @ 162\u00a0MOPS, 0.32V to 1.15V Voltage Range Multi-Core Accelerator for Energy-E\ufb03cient Parallel and Sequen<\/em><\/strong>tial Digital Processing<\/em><\/strong>,<\/a>\u201d in\u00a0 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX)<\/em>, pp. 1-3, Yokohama, April 2016<\/li>\n
      18. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, A. Burg, and A. Fish, \u201cA process compensated gain cell\u00a0embedded DRAM for ultra low power variation aware design<\/em><\/strong><\/a>,\u201d in\u00a0 2016 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1006-1009, Montreal, QC, 2016<\/li>\n
      19. R. Ghanaatian, P. Whatmough, J. Constantin, A. Teman<\/strong>, and A. Burg, \u201cA low-power correlator for wake-up receivers with algorithm pruning through early termination<\/em><\/strong><\/a>,\u201d in 2016 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 2667-2670,\u00a0 Montreal, QC, May 2016<\/li>\n
      20. R. Giterman, A. Teman<\/strong>, L. Atias, and A. Fish, \u201cA soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications<\/em><\/strong><\/a>,\u201d in Proc. of IEEE S3S<\/em> , pp. 1-2, October 2015<\/li>\n
      21. S. Ganapathy, G. Karakonstantis, A. Teman<\/strong>, and A. Burg, \u201cMitigating the impact of faults in unreliable\u00a0memories for error-resilient application<\/em><\/strong>s<\/em><\/strong><\/a>,\u201d in Proc. of the Design Automation Conference (DAC) DAC<\/em>, pp. 102:1-106:6, ACM, NY., USA,\u00a0 2015<\/li>\n
      22. S. Ganapathy, A. Teman<\/strong>, R. Giterman, A. P. Burg, and G. Karakonstantis, \u201cApproximate computing with unreliable dynamic memories<\/a>,<\/em><\/strong>\u201d in Proc. of Int. New Circuits And Systems Conference (NEWCAS)<\/em>, pp. 1-4, June 2015 Special session on Approximate Computing.<\/li>\n
      23. A. Bonetti, A. Teman<\/strong>, and A. P. Burg, \u201cAn overlap-contention free true-single-phase clock dual-edge-triggered \ufb02ip-\ufb02op<\/em><\/strong>,<\/a>\u201d in Proc. of IEEE Int. Symp. on Circuits and Systems (ISCAS), 2015<\/li>\n
      24. A. Teman<\/strong>, G. Karakonstantis, R. Giterman, P. Meinerzhagen, and A. Burg, \u201cEnergy versus data\u00a0integrity trade-o\ufb00s in embedded high-density logic compatible dynamic memories<\/em><\/strong><\/a>,\u201d in Proc. of the Design Automation and Test in Europe Conference Exhibition (DATE), DATE 2015, pp. 489\u2013494, San Jose, CA, USA, 2015<\/li>\n
      25. A. Teman<\/strong>, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, \u201cControlled placement of standard cell\u00a0memory arrays for high density and low power in 28nm FD-SOI<\/em><\/strong>,<\/a>\u201d in Proc. of the Asia and South Pacific Design Automation Conference (ASP-DAC) , pp. 81\u201386, 2015<\/li>\n
      26. L. Atias, A. Teman<\/strong> and A. Fish, \"Single event upset mitigation in low power SRAM design,\"\u00a02014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI)<\/em>, pp. 1-5, Eilat, 2014<\/li>\n
      27. R. Giterman, A. Teman<\/strong>, P. Meinerzhagen, A. Burg and A. Fish, \u201c4T gain-cell with internal-feedback\u00a0for ultra-low retention power at scaled CMOS nodes<\/a>,<\/em><\/strong>\u201din 2014 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 2177-2180, Melbourne VIC, 2014<\/li>\n
      28. A. Teman<\/strong>, \u201cDynamic Stability and Noise Margins of SRAM Arrays in Nanoscaled Technologies<\/em><\/strong><\/a>,\u201d in IEEE FTFC 2014<\/em>, pp. 1-5, Monte Carlo, Monaco<\/li>\n
      29. A. Vaknin, O. Yona and A. Teman<\/strong>, \"A Double-Feedback 8T SRAM bitcell for low-voltage low-leakage operation,\"\u00a02013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2, Monterey, CA, 2013<\/li>\n
      30. L. Atias, A. Teman<\/strong> and A. Fish, \"A 13T radiation hardened SRAM bitcell for low-voltage operation,\"\u00a02013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, pp. 1-2, Monterey, CA, 2013<\/li>\n
      31. N. Edri, S. Fraiman, A. Teman<\/strong> and A. Fish, \"Data retention voltage detection for minimizing the standby power of SRAM arrays,\"\u00a02012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 1-5, Eilat, 2012<\/li>\n
      32. A. Teman<\/strong>, P. Meinerzhagen, A. Burg and A. Fish, \"Review and classification of gain cell eDRAM implementations,\"\u00a02012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 1-5, Eilat, 2012<\/li>\n
      33. P. Meinerzhagen, A. Teman<\/strong>, A. Mordakhay, A. Burg and A. Fish, \"A sub-VT 2T gain-cell memory for biomedical applications,\"\u00a02012 IEEE Subthreshold Microelectronics Conference (SubVT)<\/em>, pp. 1-3, Waltham, MA, 2012<\/li>\n
      34. H. Dagan, A. Teman<\/strong>, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, \"A low-cost low-power non-volatile memory for RFID applications,\"\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1827-1830, Seoul, 2012<\/li>\n
      35. H. Dagan, A. Teman<\/strong>, A. Fish, E. Pikhay, V. Dayan and Y. Roizin, \"A GIDL free tunneling gate driver for a low power non-volatile memory array,\"\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 452-455, Seoul, 2012<\/li>\n
      36. J. Mezhibovsky, A. Teman<\/strong> and A. Fish, \"State space modeling for sub-threshold SRAM stability analysis,\"\u00a02012 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, pp. 1823-1826, Seoul, 2012<\/li>\n
      37. I. Schwartz, A. Teman<\/strong>, R. Dobkin and A. Fish, \"Near-threshold 40nm Supply Feedback C-element,\"\u00a02011 3rd Asia Symposium on Quality Electronic Design (ASQED)<\/em>, pp. 74-78, Kuala Lumpur, 2011<\/li>\n
      38. J. Mezhibovsky, A. Teman<\/strong> and A. Fish, \"Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM,\"\u00a02011 IEEE International SOC Conference<\/em>, pp. 136-141, Taipei, 2011<\/li>\n
      39. A. Teman<\/strong> and A. Fish, \"Sub-threshold and near-threshold SRAM design,\"\u00a02010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 000608-000612, Eilat, 2010<\/li>\n
      40. A. Teman<\/strong>, O. Yadid-Pecht and A. Fish, \"An Improved AB2C scheme for leakage power reduction in image sensors with on-chip memory,\"\u00a0SENSORS, 2009 IEEE<\/em>, pp. 193-196, Christchurch, 2009<\/li>\n
      41. S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, \"Ultra-low power subthreshold flip-flop design,\"\u00a02009 IEEE International Symposium on Circuits and Systems<\/em>, pp. 1573-1576, Taipei, 2009<\/li>\n
      42. S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and A. Fish, \"Digital subthreshold logic design - motivation and challenges,\"\u00a02008 IEEE 25th Convention of Electrical and Electronics Engineers in Israel<\/em>, pp. 702-706 , Eilat, 2008<\/li>\n
      43. A. Teman, S. Fisher, L. Sudakov, A. Fish and O. Yadid-Pecht, \"Autonomous CMOS image sensor for real time target detection and tracking,\"\u00a02008 IEEE International Symposium on Circuits and Systems<\/em>, pp. 2138-2141, Seattle, WA, 2008<\/li>\n<\/ol>\n

        Select Talks<\/strong><\/h4>\n
          \n
        1. O.\u00a0Maltabashi and A. Teman<\/strong>,\u00a0\"Controlled Placement of Standard Cell Memories with Innovus Implementation System<\/strong><\/em><\/a>\", in CDNLive Israel, October 2017<\/li>\n
        2. A. Teman<\/strong>,\u00a0\"FD-SOI Standard Cell Characterization with Cadence Liberate<\/strong><\/em><\/a>\", in CDNLive Israel, October 2016<\/li>\n
        3. A. Bonetti, N. Preyss, A. Burg, and A. Teman<\/strong>, \u201cDual-edge triggered clocking - how we can use it and when<\/em><\/strong><\/a>,\u201d in CDNLive Israel, October 2015<\/li>\n
        4. A. Bonetti, N. Preyss, A. Teman<\/strong> and A. Burg, \u201cAutomated Integration of Dual-Edge Triggered Clocking Into the Standard Design Flow<\/a><\/strong>\u00a0,\u201d in CDNLive EDMA, April 2015<\/li>\n
        5. A. Bonetti, J. Constantin, A. Teman<\/strong> and A. Burg, \u201cCircuits and techniques for dynamic timing monitoring in microprocessors<\/em><\/strong>,\u201d in Nanotera Annual Meeting 2015, May 2015<\/li>\n
        6. A. Teman<\/strong>, G. Karakonstatis, S. Ganapathy, and A. Burg, \u201cExploiting application error resilience for energy savings in memories<\/em><\/strong>,\u201d in Workshop on Approximate Computing (WAPCO), January 2015<\/li>\n
        7. A. Teman<\/strong> and A. Fish, \u201cSRAM stability in the nanoscale era<\/em><\/strong>,\u201d in CDNLive Israel, September 2012<\/li>\n
        8. A. Teman<\/strong> and A. Fish, \u201cLow voltage logic and SRAM design<\/em><\/strong><\/a>,\u201d in ChipEx 2011, May 2011<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

          Books and Book Chapters: P. Meinerzhagen, A. Teman, R. Giterman, N. Edri, A. Burg and A. Fish – \u201cGain-Cell Embedded DRAMs for Low Power VLSI Systems-on-Chip\u201d,\u00a0 Springer International Publishing, 2018. Journal Articles: R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, A. Teman and A. Burg, “Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the … Continue reading Publications<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-26","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/26"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/comments?post=26"}],"version-history":[{"count":89,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/26\/revisions"}],"predecessor-version":[{"id":453,"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/pages\/26\/revisions\/453"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/temanad\/wp-json\/wp\/v2\/media?parent=26"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}