{"id":18,"date":"2015-08-02T10:55:01","date_gmt":"2015-08-02T07:55:01","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/shorjos\/?page_id=18"},"modified":"2026-02-03T12:14:03","modified_gmt":"2026-02-03T10:14:03","slug":"patents","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/shorjos\/patents\/","title":{"rendered":"Patents"},"content":{"rendered":"

Issued US Patents:<\/h4>\n
    \n
  1. \n

    J.Shor, Y. Schifmann, I. Stanger, N. Shavit, E. R. Taco Lasso, A. Fish, \" Method for mitigation of droop timing errors including a droop detector and dual mode logic\", Mar 3, 2025, US Patent 12,261,600<\/p>\n<\/li>\n

  2. Y. Schifmann, J. Shor<\/strong>, \"Method to utilize mismatch size to produce additional stable bit in tilting PUF\", May 14, 2024. US Patent 11,985,260<\/li>\n
  3. O. Bass and J. Shor<\/strong>, \"Miniaturized digital temperature sensor\", 7 September 2021. US Patent 11,112,816<\/li>\n
  4. L. Lisha and J. Shor<\/strong>, \u201cProcess monitor circuitry with measurement capability\u201d, 7 September 2021. US Patent 11,114,352<\/li>\n
  5. J. Shor<\/strong>, Y. Weizman and Y. Shifman, \"Detecting Unreliable Bits In Transistor Circuitry\", 4 May 2021. US Patent\u00a0 10,999,083<\/li>\n
  6. J. Shor<\/strong> and N. Vinshtok-Melnik, \"Ring Oscillator Temperature Sensor\", 4 May 2021. US Patent 10,998,889<\/li>\n
  7. A. Mordakhay and J. Shor,<\/strong> \"Miniaturized Thermistor Based Thermal Sensor\", 22 December 2020. US Patent 10,871,404<\/li>\n
  8. Y. Shifman, A. Miller, J. Shor<\/strong>, \"Two bit\/cell SRAM PUF with enhanced reliability\", 24 November 2020. US Patent 10,848,327<\/li>\n
  9. J. Shor<\/strong>, R. Levi and Y. Weizman, \"Physical unclonable functions related to inverter trip points\", 21 April 2020. US Patent 10,630,493<\/li>\n
  10. K. Luria, A. Lyakhov, J. Shor<\/strong> and M. Zelikson, \"Low dropout voltage regulator integrated with digital power gate driver\", 18 December 2018. US Patent 10,156,859<\/li>\n
  11. J. Shor<\/strong>, \"Switch capacitor in bandgap voltage reference (BGREF)\", 28 August 2018. US Patent 10,061,336<\/li>\n
  12. J. Shor<\/strong>, \"Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor\", 12 June 2018. US Patent 9,996,143<\/li>\n
  13. J. Shor<\/strong>, G. Geannopoulos, F. Paillet, L. Vu, and O. Dadashev, \"Bandgap reference circuit with low output impedance stage and power-on detector\", 20 March 2018. US Patent 9,921,592<\/li>\n
  14. N. Familia, A. Saksonov, E. Fayneh, J. Shor, <\/strong>\"Digital phase-locked loop supply voltage control\", 9 January 2018. US Patent 9,866,225<\/li>\n
  15. J.Shor<\/strong>, \"Accurate power-on detector\", 2 May 2017. US Patent 9,639,133<\/li>\n
  16. N. Familia, A. Saksonov, E. Fayneh, J. Shor, <\/strong>\"Digital phase-locked loop supply voltage control\", 24 May 2016. US Patent 9,350,365<\/li>\n
  17. J. Shor,<\/strong> \"Apparatus and method for selectively disabling one or more analog circuits of a processor during a low power state of the processor\", 3 May 2016. US Patent 9,329,668<\/li>\n
  18. F. Paillet, J. Shor<\/strong>, G. L. \u00a0Geannopoulos and H. Y. Tan, \"Linear voltage regulator based on-die grid\", 15 December 2015. US Patent 9,213,382<\/li>\n
  19. K. Luria and J. Shor<\/strong>, \"Ratio meter for temperature sensor\", 20 March 2012. US Patent 8,136,987<\/li>\n
  20. J. Shor<\/strong>, A. Zaidel, N. Familia, \"Low noise voltage regulator\", 5 July 2011. US Patent 7,973,518<\/li>\n
  21. J. Shor<\/strong>, \"Power supply circuit for a phase-locked loop\", 1 June 2010. US Patent 7,728,688<\/li>\n
  22. J. Shor<\/strong> and E. Fayneh, \"Voltage regulator\", 21 July 2009. US Patent 7,564,299<\/li>\n
  23. K. Luria and J. Shor<\/strong>, \"Analog thermal sensor array\", 23 June 2009. US Patent 7,549,795<\/li>\n
  24. J.\u00a0 Tschanz,V.\u00a0 Zia, V. De , J. Shor<\/strong>, \"Bidirectional body bias regulation\", 15 July 2008. US Patent 7,400,186<\/li>\n
  25. J. Shor<\/strong>, \"Buffered cascode current mirror\", 26 February 2008. US Patent 7,336,133<\/li>\n
  26. J. Shor<\/strong>, E. Maayan and Y. Betser, \"MOS capacitor with reduced parasitic capacitance\", 14 August 2007. US Patent 7,256,438<\/li>\n
  27. J. Shor<\/strong>, Y Betser and Y. Sofer, \"Power-up and BGREF circuitry\", 13 March 2007. US Patent 7,190,212<\/li>\n
  28. J. Shor<\/strong> and E. Maayan, \"Charge pump element with body effect cancellation for early charge pump stages\", 12 December 2006. US Patent 7,148,739<\/li>\n
  29. J. Shor<\/strong> and Y. Betser, \"Class AB voltage regulator\", 26 July 2005. US Patent 6,922,099<\/li>\n
  30. J. Shor<\/strong> and Y. Polansky, \"Fast discharge for program and verification\", 14 June 2005. US Patent 6,906,966<\/li>\n
  31. J. Shor<\/strong>, \"Operational amplifier with fast rise time\", 26 April 2005. US Patent 6,885,244<\/li>\n
  32. J. Shor<\/strong>, E. Maayan and Y. Polansky, \"Charge pump stage with body effect minimization\", 8 March 2005. US Patent 6,864,739<\/li>\n
  33. J. Shor<\/strong>, A. Harush and S. Eisen, \"Method and circuit for operating a memory cell using a single charge pump\", 11 January 2005. US Patent 6,842,383<\/li>\n
  34. J. Shor<\/strong> and E. Maayan, \"Stack element circuit\", 14 September 2004. US Patent 6,791,396<\/li>\n
  35. J. Shor<\/strong> and E. Maayan, \"Charge pump stage with body effect minimization\", 13 January 2004. US Patent 6,677,805<\/li>\n
  36. J. Shor<\/strong>, Y. Sofer and E. Maayan, \"Charge pump with constant boosted output voltage\", 10 June 2003. US Patent 6,577,514<\/li>\n
  37. J. Shor<\/strong>, Y. Sofer and E. Maayan, \"Voltage regulator for non-volatile memory with large power supply rejection ration and minimal current drain\", 10 September 2002. US Patent 6,448,750<\/li>\n
  38. J. Shor<\/strong>, V. Koifman and Y. Afek, \"Circuit arrangement to compensate non-linearities in a resistor, and method\", 26 December 2000. US Patent 6,166,578<\/li>\n
  39. J. Shor<\/strong>, A.D. Kurtz and D. Goldstein, \"Method for etching of silicon carbide semiconductor using selective etching of different conductivity types\", 7 March 2000. US Patent 6,034,001<\/li>\n
  40. J. Shor<\/strong>, M. Yosefin and D. Bruck, \"Circuit with hot-electron protection and method\", 5 October 1999. US Patent 5,963,076<\/li>\n
  41. M. Yosefin, Y. Afek and J. Shor<\/strong>, \"Circuit with hot electron protection and method\", 14 September 1999. US Patent 5,952,875<\/li>\n
  42. J. Shor<\/strong>, E. Engel and N. Baron, \"Apparatus and method for shifting signal levels\", 12 May 1998. US Patent 5,751,178<\/li>\n
  43. A.D. Kurtz, J. Shor<\/strong> and A. Ned, \"Method for forming isolated CMOS structures on SOI structures\", 28 January 1997. US Patent 5,597,738<\/li>\n
  44. J. Shor<\/strong> and A.D. Kurtz, \"Porous silicon carbide (SIC) semiconductor device\", 29 October 1996. US Patent 5,569,932<\/li>\n
  45. A.D. Kurtz, J. Shor<\/strong> and A. Ned, \"Method for making semiconductor structures having environmentally isolated elements\", 24 October 1995. US Patent 5,461,001<\/li>\n
  46. J. Shor<\/strong> and A.D. Kurtz, \"Method of fabricating porous silicon carbide (SiC)\", 3 October\u00a0 1995. US Patent 5,454,915<\/li>\n
  47. A.D. Kurtz, J. Shor<\/strong> and A. Ned, \"Semiconductor structures having environmentally isolated elements and method for making the same\", 31 January 1995. US Patent 5,386,142<\/li>\n
  48. J. Shor<\/strong> and A.D. Kurtz, \"Fabricating porous silicon carbide\", 27 December 1994. US Patent 5,376,241<\/li>\n
  49. A.D.Kurtz and J. Shor<\/strong>, \"Pressure transducer utilizing diamond piezoresistive sensors and silicon carbide force collector\", 19 April 1994. US Patent 5,303,594<\/li>\n
  50. J. Shor<\/strong> and A.D. Kurtz, \"Porous silicon carbide (SiC) semiconductor device\", 29 March 1994. US Patent 5,298,767<\/li>\n
  51. A.D. Kurtz, D. Goldstein and J. Shor<\/strong>, \"High temperature transducers and methods of fabricating the same employing silicon carbide\", 24 November 1992. US Patent 5,165,283<\/li>\n<\/ol>\n

    Pending US Patent \/ Application # \/ Inventors<\/b><\/h4>\n","protected":false},"excerpt":{"rendered":"

    Issued US Patents: J.Shor, Y. Schifmann, I. Stanger, N. Shavit, E. R. Taco Lasso, A. Fish, ” Method for mitigation of droop timing errors including a droop detector and dual mode logic”, Mar 3, 2025, US Patent 12,261,600 Y. Schifmann, J. Shor, “Method to utilize mismatch size to produce additional stable bit in tilting PUF”, … Continue reading Patents<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-18","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/pages\/18"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/comments?post=18"}],"version-history":[{"count":85,"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/pages\/18\/revisions"}],"predecessor-version":[{"id":719,"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/pages\/18\/revisions\/719"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/shorjos\/wp-json\/wp\/v2\/media?parent=18"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}