{"id":40,"date":"2012-05-09T23:12:58","date_gmt":"2012-05-09T20:12:58","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/kereno\/?page_id=40"},"modified":"2022-05-03T14:38:51","modified_gmt":"2022-05-03T11:38:51","slug":"patents","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/kereno\/patents\/","title":{"rendered":"Patents"},"content":{"rendered":"<ul>\n<li>A. Fish, <strong>O. Keren<\/strong>, Y. Weizman and M. Elkoni, \u201cInformation Redistribution to reduce side channel leakage\u201d, US Patent No. 11,321,460, granted May 2022.<\/li>\n<li>I. Levi, <strong>O. Keren<\/strong> and A. Fish, \"Pseudo-Asynchronous digital circuit design\",\u00a0 U.S. Patent No: 11,023,632 , granted June 2021.<\/li>\n<li>M. Avital, I. Levi, A. Fish, O. Keren, \"Randomized logic against side channel attacks\", US patent No.: 10,951,39, granted, Mar. 16, 2021<\/li>\n<li>I. Levi, <strong>O. Keren<\/strong>, and A. Fish. \"Pseudo-asynchronous digital circuit design\". U.S. Patent 10,572,619, granted Feb. 25, 2020.<\/li>\n<li>I. Levi, <strong>O. Keren<\/strong> and A. Fish, \"Data-dependent delay circuits\", US Patent:\u00a0 10,521,530 granted December 2019.<\/li>\n<li>H. Rabii, Y. Neumeier, Y. Bodner, T. Sdika and <strong>O. Keren<\/strong>, \"Separable robust coding\", US 2019-0259466, Aug 2019.<\/li>\n<li>M. Avital, A. Fish, H. Dagan, <strong>O. Keren<\/strong>, \"Multi-topology logic gates\", US patent No: 10,169,617, granted January 2019.<\/li>\n<li>R. Giterman, I. Levi, <strong>O. Keren<\/strong>, and<strong>\u00a0<\/strong>A. Fish, \u201cSecured memory\u201d, PCT application No: PCT\/IL2018\/051338, US 16\/769,664, December 2018.<\/li>\n<li>A. Fish, M. Avital, A. Mordakhay, Y. Weizman and <strong>O. Keren<\/strong>, \u201cCompact Bit Generator\u201d, Application No.: US 16\/224,869, December 2018.<\/li>\n<li>E. Ofek and <strong>O. Keren<\/strong>, \"Scalar product and parity check\", United States Patent 6760880 , filing date 08.1999 publication date 06.2004.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>A. Fish, O. Keren, Y. Weizman and M. Elkoni, \u201cInformation Redistribution to reduce side channel leakage\u201d, US Patent No. 11,321,460, granted May 2022. I. Levi, O. Keren and A. Fish, &#8220;Pseudo-Asynchronous digital circuit design&#8221;,\u00a0 U.S. Patent No: 11,023,632 , granted June 2021. M. Avital, I. Levi, A. Fish, O. Keren, &#8220;Randomized logic against side channel &hellip; <a href=\"https:\/\/www.eng.biu.ac.il\/kereno\/patents\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Patents<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-40","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/pages\/40"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/comments?post=40"}],"version-history":[{"count":36,"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/pages\/40\/revisions"}],"predecessor-version":[{"id":526,"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/pages\/40\/revisions\/526"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/kereno\/wp-json\/wp\/v2\/media?parent=40"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}