{"id":246,"date":"2016-09-07T15:13:42","date_gmt":"2016-09-07T12:13:42","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/fishale\/?page_id=246"},"modified":"2021-06-02T14:36:36","modified_gmt":"2021-06-02T11:36:36","slug":"conference-papers","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/fishale\/publications\/conference-papers\/","title":{"rendered":"Conferences"},"content":{"rendered":"<h4 style=\"text-align: justify\"><strong>Conference papers<\/strong><\/h4>\n<p style=\"text-align: justify\"><strong>2018-2021<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li>I. Stanger, N. Shavit, R. Taco, M. Lanuzza, A. Fish, \u201cLive Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths\u201d, <em>2021 IEEE International Symposium on Circuits and Systems (ISCAS), hybrid<\/em><\/li>\n<li>N. Shavit, I. Stanger, R. Taco, M. Lanuzza, A. Fish, \u201cLive Demonstration: A 0.8V, 1.54 pJ \/ 940 MHz Dual Mode Logic-based 16x16-bit Booth Multiplier in 16-nm FinFET\u201d, <em>2021 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, hybrid<\/li>\n<li>I. Stanger, N. Shavit, R. Taco, M. Lanuzza and <strong>A. Fish<\/strong>, \"Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths\" <em>ISICAS- IEEE Symposium on Integrated Circuits and Systems 2020, <\/em>Shanghai, China, 2020<\/li>\n<li>M. Assaf, O. Harel, E. Tadmor, O. Yadid Pecht and <strong>A. Fish<\/strong>, \"Weight Based Current Assisted Photonic Demodulator (WBCAPD) - Expansion Towards Neuromorphic Applications\" <em>2020 IEEE International Symposium on Circuits and Systems (ISCAS),\u00a0 <\/em>Seville, Spain, 2020<\/li>\n<li>R. Taco, L. Yavits, N. Shavit, I. Stanger, M. Lanuzza, <strong>A. Fish<\/strong>, \"Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic \u2013Based Digital Circuits in 28nm FD-SOI Technology\" <em>2020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>,\u00a0 Seville, Spain, 2020<\/li>\n<li>L. Yavits, R. Taco, N. Shavit, I. Stanger and <strong>A. Fish<\/strong>, \"Dual Mode Logic Address Decoder\" <em>2020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>,\u00a0 Seville, Spain, 2020<\/li>\n<li>I. Stanger, N. Shavit, R. Taco, L. Yavits, M. Lanuzza and <strong>A. Fish<\/strong>, \"Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance\"\u00a0<em>2020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>,\u00a0 Seville, Spain, 2020<\/li>\n<li>D. Zooker, M. Elkoni, O. Ohev Shalom, Y. Weizman, I. Levi, O. Keren and <strong>A. Fish<\/strong>, \"Temporal Power Redistribution as a Countermeasure Against Side-Channel Attacks\" <em>2020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>,\u00a0 Seville, Spain, 2020<\/li>\n<li>R. Giterman, M. Wicentowski, O. Chertkow, I. Sever, I. Kehati, Y. Weizman, O. Keren and <strong>A. Fish<\/strong>, \"Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications,\" <em>ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)<\/em>, Cracow, Poland, 2019, pp. 69-72<\/li>\n<li>D. Zooker, A. Fish, O. Keren and Y. Weizman, \"Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications,\" <em>2019 10th IFIP International Conference on New Technologies, Mobility and Security (NTMS)<\/em>, pp. 1-5, CANARY ISLANDS, Spain, 2019<\/li>\n<li>D. Zooker, <strong>A. Fish<\/strong>, O. Keren, \"DPMUX Based LUT Towards Secure FPGA\", <em>TRUDEVICE Workshop<\/em>, Baden Baden, Germany 2019.<\/li>\n<li>I. Kehati, M. Vicentowski, R. Giterman, Y. Weizman, <strong>A. Fish<\/strong>, O. Keren, \"Demonstration of dynamic write cycle power analysis attacks against SRAM implementations\", <em>TRUDEVICE Workshop 2019<\/em>, Baden Baden, Germany 2019.<\/li>\n<li>R. Taco, I. Levi, M. Lanuzza and <strong>A. Fish<\/strong>, \"Live Demo: An 88fJ \/ 40 MHz [0.4V] \u2013 0.61pJ \/ 1GHz [0.9V] Dual Mode Logic 8\u00d78-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI,\"\u00a0<em>2019 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, Sapporo, Japan, 2019, pp. 1-1.<\/li>\n<li>Y. Shifman, A. Miller, Y. Weizman, <strong>A. Fish<\/strong> and Joseph Shor, \u201cAn SRAM PUF with 2 Independent Bits\/Cell in 65nm\u201d, <em>2019 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, Sapporo, Japan, 2019, pp. 1-5.<\/li>\n<li>Y. Rudin, I. Levi, <strong>A. Fish<\/strong> and O. Keren, \"FPGA Implementation of pAsynch Design Paradigm,\" <em>2019 10th IFIP International Conference on New Technologies, Mobility and Security (NTMS)<\/em>, CANARY ISLANDS, Spain, 2019, pp. 1-5.<\/li>\n<li>D. Zooker, <strong>A. Fish<\/strong>, O. Keren and Y. Weizman, \"Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications,\" <em>2019 10th IFIP International Conference on New Technologies, Mobility and Security (NTMS)<\/em>, CANARY ISLANDS, Spain, 2019, pp. 1-5.<\/li>\n<li>A. Shalom, A. Fish and A. Teman, \"A 9pW\/bit 440mV 3T Gain-Cell eDRAM for ULP Applications in 28nm FD-SOI\" in <em>Proc. of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, October 2019<\/li>\n<li>R. Giterman, A. Teman and <strong>A. Fish, <\/strong>\"A 14.3 pW Sub-Threshold 2T Gain-Cell eDRAM for Ultra-Low Power IoT Applications in 28nm FD-SOI.\"\u00a0<em>2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>. IEEE, 2018.<\/li>\n<li>R Giterman, O. Keren and <strong>A. Fish<\/strong>, \"Improving the Security of a 6T SRAM using Body-Biasing in 28 nm FD-SOI.\"\u00a0<em>2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>. IEEE, 2018.<\/li>\n<li>N. Shavit, R. Taco and <strong>A. Fish<\/strong>, \"Efficiency of Dual Mode Logic in Nanoscale Technology Nodes,\" <em>2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE)<\/em>, Eilat, Israel, 2018, pp. 1-4.<\/li>\n<li>N. Shavit, I. Stanger, R. Taco and <strong>A. Fish<\/strong>, \"Process Variation-Aware Data path Employing Dual Mode Logic,\"\u00a0<em>2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)<\/em>, Burlingame, CA, USA, 2018, pp.\u00a01-3.<\/li>\n<li>M. Avital,\u00a0<strong>A. Fish<\/strong>, A. Mordakhay, D. Zooker, Y. Weizman and O. Keren,\u00a0 \u00a0 \"Utilization of Process and Supply Voltage Random Variations for Random Bit Generation\", <em>2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)<\/em>, Chengdu, China, October 2018.<\/li>\n<li>M. Avital, I. Levi, Y. Rudin, <strong>A. Fish<\/strong> and O. Keren, \"Embedded Randomness and Data Dependencies Design Paradigm: Advantages and Challenges\", a<em>ccepted for presentation at DATE conference<\/em>, Dresden, Germany, March, 2018.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2017<\/strong><strong>-2015<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li style=\"list-style-type: none\"><\/li>\n<li>U. Zangi, N. Feldman, J. Shor and <strong>A. Fish<\/strong>, \u201c0.45v and 18\u03bcA\/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)\u201d, <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2017 (Best Paper Finalist).<\/li>\n<li>R. Giterman, A. Teman and <strong>A. Fish<\/strong>, \u201cA 11.5pW\/bit 400mV 5T Gain-Cell eDRAM for ULP Applications in 28nm FD-SOI\u201d, <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2017.<\/li>\n<li>R. Taco, I. Levi, M. Lanuzza and <strong>A. Fish<\/strong>, \u201cEnergy-Delay Tradeoffs of Low-Voltage Dual Mode Logic in 28nm FD-SOI\u201d, <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2017.<\/li>\n<li>D. Zooker, I. Levi, <strong>A Fish<\/strong> and O. Keren, \u201cSecured Dual-Rail-Precharge Mux-Based (DPMUX) Symmetric-Logic for Low Voltage Applications\u201d, <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2017.<\/li>\n<li>M. Haber, I. Levi and <strong>A. Fish<\/strong>, \u201cDifferential Input Output CMOS (DINO-CMOS) \u2013High performance and Energy Efficient Logic Family\u201d, <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2017.<\/li>\n<li>Y. Shoshan, S. Yuzhaninov, N. Edri, S. Harai, Y. Rudin, Y. Weizman, I. Nadler, N. Rosenberg, B. Flom, D. Bechor, G. Morag, E. Grigoriants, N. Blum, R. Daly, M. Reuveni and <strong>A. Fish<\/strong>, \u201cA SoC Platform for Emerging Technologies\u201d, <em>Proc. IEEE ISOSOC conference<\/em>, Seoul, South Korea, October 2017.<\/li>\n<li>R. Giterman, <strong>A. Fish<\/strong>, N. Geuli, E. Mentovich, A. Burg and A. Teman, \u201cAn 800 Mhz Mixed-VT 4T Gain-Cell Embedded DRAM in 28nm CMOS Bulk Process for Approximate Computing Applications\u201d, <em>Proc IEEE ESSCIRC conference<\/em>, Belgium, September 2017.<\/li>\n<li>D. Zooker, M. Vizentovski, Y. Weizman, <strong>A. Fish<\/strong> and O. Keren, \u201cVulnerability of Secured IoT Memory Against Localized Back Side Laser Fault Injection\u201d, <em>Seventh IEEE International\u00a0Conference\u00a0on Emerging Security Technologies<\/em>, UK, September 2017.<\/li>\n<li>I. Levi, <strong>A. Fish<\/strong> and O. Keren, \u201cSecurity Aware Pseudo-Asynchronous Circuit Design Style \u201c, <em>2nd IEEE International Verification and Security Workshop<\/em>, Greece, July 2017.<\/li>\n<li>R. Taco, I. Levi, M. Lanuzza and <strong>A. Fish<\/strong>, \"Evaluation of Dual Mode Logic in 28nm FD-SOI Technology, <em>accepted for oral presentation at IEEE ISCAS 2017<\/em>.<\/li>\n<li>O. Bass, R. Giterman, <strong>A. Fish<\/strong> and D. Naveh, \u201cTranmistor-only Based Crossbar Memory Array with a Two Stage Readout Scheme\u201d, <em>Proc. MEMRYS conference<\/em>, Greece, March 2017.<\/li>\n<li>O. Bass, R. Giterman, <strong>A. Fish<\/strong> and D. Naveh, \"A Device-Level Approach to Resolving the Sneak Currents of Crossbar Arrays\", accepted for presentation at International Conference on Memristive Materials, Devices &amp; Systems (MEMRISYS 2017), Greece, April 2017.<\/li>\n<li>M. Avital, <strong>A. Fish<\/strong> and O. Keren, \"From Full-Custom to Fully-Standard Cell Power Analysis Countermeasures\", <em>Truedevice workshop<\/em>, Barcelona, November 2016.<\/li>\n<li>R. Giterman, A. Teman, P. Meinerzhagen, <strong>A. Fish<\/strong>, and A. Burg, \"A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design\", a<em>ccepted to IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>R. Taco, I. Levi, M. Lanuzza and <strong>A. Fish<\/strong>, \"Extended Exploration of Low Granularity Back Biasing Control in 28nm UTBB FD-SOI Technology\", <em>accepted to IEEE ISCAS, Montreal<\/em>, Canada, May 2016.<\/li>\n<li>R. Taco, I. Levi, M. Lanuzza and <strong>A. Fish<\/strong>, \"Low voltage Ripple Carry Adder with low-Granularity Dynamic Forward Back-Biasing in 28 nm UTBB FD-SOI\", <em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2015.<\/li>\n<li>R. Giterman, A. Teman and <strong>A. Fish<\/strong>, \" A Soft Error Tolerant 4T Gain-Cell Featuring a Parity Column for Ultra-Low Power Applications\", \u00a0<em>Proc. IEEE S3S conference<\/em>, San Francisco, USA, October 2015.<\/li>\n<li>E. Tadmor, A. Nevet, G. Yahav, <strong>A. Fish<\/strong> and D. Cohen, \"A Fast Gated CMOS Image Sensor with a Vertical Overflow Drain Shutter Mechanism\", <em>2015 International Image Sensor Workshop,<\/em> Vaals, Netherlands. June, 2015.<\/li>\n<li>M. Haber, B. Frankel, M. Avital, I. Levi, O. Keren and <strong>A. Fish<\/strong>, \"Insights into the\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Correlation between the Processed Data and its Power Traces\", <em>Truedevice,<\/em> France, Date 2016.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2014-2013<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li>R. Giterman and <strong>A. Fish<\/strong>, \"Towards a Black-Box Methodology for SRAM Stability Analysis\", <em>Proc. IEEEI 2014 conference<\/em>, pp. 1-4, Eilat, Israel, December 2014.<\/li>\n<li>R. Taco, I. Levi, <strong>A. Fish<\/strong> and M. Lanuzza, \"Exploring Back Biasing Opportunities in 28nm UTBB FD-SOI Technology for Subthreshold Digital Design\", <em>Proc. IEEEI 2014 conference<\/em>, PP. 1-4, Eilat, Israel, December 2014.<\/li>\n<li>L. Atias, A. Teman and <strong>A. Fish<\/strong>, \"Low Power Radiation Hardened SRAM - Challenges and Leading Solutions, <em>Proc. IEEEI 2014 conference<\/em>, PP. 1-4, Eilat, Israel, December 2014.<\/li>\n<li>A. Pescovsky, O. Chertkow, L. Atias and <strong>A. Fish<\/strong>, \u201cSEU Hardening: Incorporating an Extreme Low Power Bitcell Design (SHIELD)\u201d, <em>Proc. IEEE S3S conference<\/em>, PP. 1-3, Millbrae, USA, October 2014 (<strong>Best student paper award<\/strong>).<\/li>\n<li>R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and <strong>A. Fish<\/strong>, \u201c4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes\u201d, <em>Proc. IEEE ISCAS conference<\/em>, pp. 2177-2180, Melbourne, Australia, June 2014.<\/li>\n<li>M. Avital and <strong>A. Fish<\/strong>, \u201cSecured Dual Mode Logic (DML) as a Countermeasure Against Differential Power Analysis\u201d, <em>Proc. IEEE ISCAS 2014 conference<\/em>, pp. 810-813, Melbourne, Australia, June 2014.<\/li>\n<li>A. Mordakhay and <strong>A. Fish<\/strong>, \u201cAnalog Readout Circuit for Zero Leakage Planar-Hall-Effect-Magnetic-Random-Access-Memory\u201d, <em>Proc. IEEE FTFC 2014 conference<\/em>, pp. 1-4, Monaco, May 2014.<\/li>\n<li>R. Buzilo, B. Likhtrov, R. Giterman, I. Levi, <strong>A. Fish<\/strong> and A. Belenky, \u201cApproach to Integrated Energy Harvesting Voltage Source Based on Novel Active TEG Array System\u201d, <em>Proc. IEEE FTFC 2014 conference<\/em>, pp. 1-4, Monaco, May, 2014.<\/li>\n<li>L. Atias, A. Teman and\u00a0<strong>A. Fish<\/strong>, \u201cA 13T Radiation Hardened SRAM Bitcell for Low-Voltage Operation\u201d, <em>Proc. IEEE S3S conference<\/em>, Monterey, USA, October 2013.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2012-2011<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li>A. Teman, P. Meinerzhagen, A. Burg and <strong>A. Fish<\/strong>, \u201cReview and Classification of Gain Cell eDRAM Implementations\u201d, <em>Proc. IEEEI 2012 conference<\/em>, pp. 1-5, Eilat, Israel, November 2012.<\/li>\n<li>N. Edri, S. Fraiman, A. Teman and <strong>A. Fish<\/strong>, \u201cData Retention Voltage Detection for Minimizing the Standby Power of SRAM Arrays\u201d, <em>Proc. \u00a0IEEEI 2012 conference<\/em>, pp. 1-5, Eilat, Israel, November 2012.<\/li>\n<li>P. Meinerzhagen, A. Teman, A. Mordakhay, A. Burg and <strong>A. Fish<\/strong>, \u201cA Sub-VT 2T Gain-Cell Memory for Biomedical Applications\u201d, <em>Proc. IEEE 2012 Subthreshold Microelevctronics conference<\/em>, pp. 1-3, Waltham, USA, October 2012.<\/li>\n<li>N. Krihely, S. Ben-Yaakov and <strong>A. Fish<\/strong>, \u201cOptimization of a Multi- Target Voltages Switched Capacitor Converter\u201d, <em>Proc. International conference on Optimization of electrical and Electronic Equipment<\/em>, pp. 759-763 , Brasov, Romania, May 2012.<\/li>\n<li>H. Dagan, A. Teman, E. Pikhay, V. Dayan, Y. Roizin and <strong>A. Fish<\/strong>, \u201cA GIDL Free Tunneling Gate Driver for a Low Power Non-Volatile Memory Array\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems conference<\/em>, pp. 452-455, Seoul, Korea, May 2012.<\/li>\n<li>H. Dagan, A. Teman, E. Pikhay, V. Dayan, Y. Roizin and <strong>A. Fish<\/strong>, \u201cA Low-Cost Low-Power Non-Volatile Memory for RFID Applications\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems conference<\/em>, pp. 1827-1830, Seoul, Korea ,May 2012.<\/li>\n<li>I. Levi, O. Bass, A. Kaizerman, A. Belenky and <strong>A. Fish<\/strong>, \u201cHigh Speed Dual Mode Logic Carry Look Ahead Adder\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems conference<\/em>, pp. 3037-3040 ,Seoul, Korea, May 2012.<\/li>\n<li>J. Mezhibovsky, A. Teman, and <strong>A. Fish<\/strong>, \u201cState Space Modeling for Sub-Threshold SRAM Stability Analysis\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems conference<\/em>, pp. 1823-1826, Seoul, Korea, May 2012.<\/li>\n<li>J. Mezhibovsky, A. Teman and <strong>A. Fish, \u201c<\/strong>Low Voltage SRAMs and the Scalability of\u00a0\u00a0\u00a0\u00a0 the 9T Supply Feedback SRAM\u201d, <em>Proc. IEEE SOCC conference<\/em>, pp. 136-141, Taipei, China, September 2011.<\/li>\n<li>I. Schwartz, A. Teman, R. Dobkin and <strong>A. Fish<\/strong>, \u201cNear-Threshold 40nm Supply Feedback C-Element\u201d, <em>Proc. of the 3rd Asia Symposium On Quality Electronic Design (ASQED)<\/em>, pp. 74-78, Kuala Lumpur, Malaysia, July 2011.<\/li>\n<li>S. Fisher, R. Dagan, S. Blonder and <strong>A. Fish<\/strong>, \u201cAn Improved Model for Delay\/Energy Estimation in Near-Threshold Flip-Flops\u201d, <em>Proc. IEEE ISCAS 2011 conference<\/em>, pp. 1065-1068, Rio de Janeiro ,Brazil, May 2011.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2010-2008<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li>A. Teman and <strong>A. Fish<\/strong>, \u201cSub-threshold and Near-threshold SRAM Design\u201d, <em>Proc. IEEEI 2010 conference<\/em>, pp. 608-612, Eilat, Israel, November 2010.<\/li>\n<li>A. Morgenshtein, I. Shwartz and <strong>A. Fish<\/strong>, \u201cGate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process\u201d, <em>Proc. IEEEI 2010 conference<\/em>, pp. 777-780, Eilat, Israel, November 2010.<\/li>\n<li>D. Shurin, E. Kvaktun and <strong>A. Fish<\/strong>, \u201cInput Vector Control Efficiency in Sub-Micron CMOS Technologies\u201d <em>Proc. IEEEI 2010 conference<\/em>, pp. 569-573, Eilat, Israel, November 2010.<\/li>\n<li>A. Teman, O. Yadid-Pecht and <strong>A. Fish<\/strong>, \"An Improved AB2C Scheme for Leakage Power Reduction in Image Sensors with On-Chip Memory\", <em>Proc. IEEE Sensors Conference<\/em>, pp. 193-196, Christchurch, New Zealand, October 2009.<\/li>\n<li>S. Fisher, A. Teman, D. Vaysman, A. Gertsman,\u00a0O. Yadid-Pecht and <strong>A. Fish<\/strong>, \"Ultra-Low Power Subthreshold Flip Flop Design\", <em>Proc. ISCAS 2009<\/em>, pp. 1573-1576<em>, <\/em>Taipei, China, May 2009.<\/li>\n<li>S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O. Yadid-Pecht and <strong>A. Fish<\/strong>, \"Digital Subthreshold Logic Design \u2013 Motivation and Challenges\", <em>Proc. IEEE 2008 conference<\/em>, pp. 702-706, Eilat, Israel, December 2008.<\/li>\n<li>M. Beiderman, T. Tam, <strong>A. Fish<\/strong>, G. A. Jullien and O. Yadid-Pecht, \u201cAn advanced CMOS Imager Employing Modified AR and ACS methods\u201d, <em>Proc. IEEE Sensors conference<\/em>, pp. 1386-1389, Lecce, Italy, October 2008.<\/li>\n<li>X. Li, Y. Shoshan, <strong>A. Fish<\/strong>, G. A. Jullien and O. Yadid-Pecht, \"Hardware Implementation of a DCT Watermark for CMOS Image Sensors\", <em>Proc. IEEE International Conference on Electronics, Circuits and Systems<\/em>, pp. 368-371, St. Julien's, USA, August 2008.<\/li>\n<li>X. Li, Y. Shoshan, <strong>A. Fish<\/strong>, and G. A. Jullien, \"A Simplified Approach for Designing Secure Random Number Generators in HW\", <em>Proc. IEEE International Conference on Electronics, Circuits and Systems<\/em>, pp. 372-375, St. Julien's, USA, September 2008.<\/li>\n<li>A. Teman, S. Fisher, L. Sudakov, <strong>A. Fish<\/strong> and O. Yadid-Pecht, \"Autonomous CMOS Image Sensor for Real Time Targets Detection and Tracking\", <em>Proc. IEEE International Symposium on Circuits and Systems,<\/em> pp. 2138-2141<em>, <\/em>Seattle, USA, May 2008.<\/li>\n<li>M. Beiderman, T. Tam, <strong>A. Fish<\/strong>, G. A. Jullien and O. Yadid-Pecht, \u201cA Low Noise CMOS Image Sensor with an Emission Filter for Fluorescence Applications\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems,<\/em> pp. 1100-1103, Seattle, USA, May 2008.<\/li>\n<li><strong>A. Fish<\/strong> and O. Yadid-Pecht, \u201cLow Power \u201cSmart\u201d CMOS Image Sensors\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, pp. 1408-1411<em>, <\/em>Seattle, USA, May 2008.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2007-2005<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li><strong>A. Fish<\/strong>, O. Yadid-Pecht and E. Culurciello, \"Responsivity of Gated Photodiode in Silicon-on-Sapphire Technology\", <em>Proc. IEEE Sensors conference<\/em>, pp. 527-530, Atlanta, USA, October 2007.<\/li>\n<li><strong>A. Fish<\/strong>, T. Rothschild, A. Hodes, Y. Shoshan and O. Yadid-Pecht, \u201cLow Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB<sup>2<\/sup>C) Approach\u201d, Proc. IEEE International Symposium on Circuits and Systems, pp. 2834-2837, New-Orleans, USA, May 2007.<\/li>\n<li>A. Belenky, <strong>A. Fish<\/strong> and O. Yadid-Pecht, \"Global Shutter CMOS Image Sensor with Wide Dynamic Range\", <em>Proc. IEEE International Conference on Electronics, Circuits and Systems,<\/em> pp. 314\u2013317, Nice, France, December 2006.<\/li>\n<li><strong> A. Fish<\/strong>, S. Hamami and O. Yadid-Pecht, \"Self-Powered Active Pixel Sensors for Ultra Low-Power Applications\",<em> Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 5, pp. 5310\u20135313, Kobe, Japan, May 2005. <strong><em><u>(Best Paper Finalist Award)<\/u><\/em><\/strong>.<\/li>\n<li><strong> A. Fish<\/strong>, E. Avner and O. Yadid-Pecht, \"Low-Power Global\/Rolling Shutter Image Sensors in Silicon on Sapphire Technology\", <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 1, pp. 580-583, Kobe, Japan, May 2005.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2004<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li><strong style=\"line-height: 1.5\">A. Fish<\/strong><span style=\"line-height: 1.5\">, V. Mosheyev, V. Linkovsky and O. Yadid-Pecht, \"Ultra Low-Power DFF based Shift Registers Design for CMOS Image Sensors Applications\", <em>Proc. IEEE International Conference on Electronics, Circuits and Systems<\/em><\/span><em style=\"line-height: 1.5\">,<\/em><span style=\"line-height: 1.5\"> pp. 658\u2013661, Tel-Aviv, Israel, December 2004.<\/span><\/li>\n<li><strong>A. Fish<\/strong>, A. Spivakovsky, A. Golberg and O. Yadid-Pecht, \u201cVLSI Sensor for multiple targets detection and tracking\u201d, <em>Proc. IEEE International Conference on Electronics, Circuits and Systems<\/em>, pp. 543\u2013546, Tel-Aviv, Israel, December 2004. <strong><em><u>(Best Paper Finalist Award)<\/u><\/em><\/strong><\/li>\n<li><strong> A. Fish<\/strong>, V. Milrud and O. Yadid-Pecht, \u201cHigh speed and high resolution current Loser-take-all circuit of o(N) complexity\u201d, <em>Proc. IEEE International Conference on Electronics, Circuits and Systems<\/em>, pp. 234\u2013237, Tel-Aviv, Israel, December 2004.<\/li>\n<li><strong> A. Fish<\/strong>, A. Belenky and O. Yadid-Pecht, \u201cLow Power Global Shutter CMOS Active Pixel Image Sensor with Ultra-High Dynamic Range\u201d, <em>Proc. IEEE International Conference on Electronics, Circuits and Systems,<\/em> pp. 149\u2013152, Tel-Aviv, Israel, December 2004.<\/li>\n<li><strong> A. Fish<\/strong>, V. Milrud and O.Yadid-Pecht, \u201cHigh speed and high resolution current winner-take-all circuit in conjunction with adaptive thresholding\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 4, pp. 852-855, Vancouver, Canada, May 2004.<\/li>\n<li>A. Belenky, <strong>A. Fish<\/strong>, S. Hamami, V. Milrud and O. Yadid-Pecht, \u201cWidening the dynamic range of the readout integration circuit for uncooled micro-bolometer infrared sensors\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 5, pp. 600-603, Vancouver, Canada May, 2004.<\/li>\n<li>A. Morgenshtein, <strong>A. Fish<\/strong> and I. A. Wagner, \u201cAn efficient implementation of D-FLIP-FLOP using the GDI technique\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 2, pp. 673-676, Vancouver, Canada, May 2004.<\/li>\n<\/ol>\n<p style=\"text-align: justify\"><!--more--><\/p>\n<p style=\"text-align: justify\"><strong>2003-2002<\/strong><\/p>\n<ol style=\"text-align: justify\">\n<li><strong style=\"line-height: 1.5\">A. Fish<\/strong><span style=\"line-height: 1.5\">, D. Akselrod and O. Yadid-Pecht, \u201cAn adaptive center of mass detection system employing a 2-D dynamic element matching algorithm for object tracking\u201d, special session on Sensor Arrays for Visual Tracking and Navigation, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 3, pp. 778-781, Bangkok, Thailand, May 2003.<\/span><\/li>\n<li>D. Askelrod, <strong>A. Fish<\/strong> and O. Yadid-Pecht, \"A Mixed Signal Enhanced WTA Tracking System via 2D Dynamic Element Matching\", <em>Proc. IEEE International Symposium on Circuits and Systems,<\/em> vol. 3, pp. 755-758, Arizona, USA, May 2002.<\/li>\n<li><strong>A. Fish<\/strong>, D. Turchin and O. Yadid-Pecht, \"An APS with 2D WTA Selection Employing Adaptive Spatial Filtering, Bad Pixel Elimination and False Alarm Reduction\", <em>Proc. IEEE International Symposium on Circuits and Systems,<\/em> vol. 2, pp. 328-331, Arizona, USA, May 2002.<\/li>\n<li>A. Morgenshtein, <strong>A. Fish<\/strong> and I. A. Wagner, \u201cGate-diffusion input (GDI) \u2013 a technique for low power design of digital circuits: analysis and characterization\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems<\/em>, vol. 1, pp. 477-480, Arizona, USA, May 2002.<\/li>\n<li>A. Morgenshtein, <strong>A. Fish<\/strong> and I. A. Wagner, \u201cGate-Diffusion Input (GDI) \u2013 A Novel Power Efficient Method for Digital Circuits: A Detailed Methodology\u201d, <em>Proc. IEEE International ASIC\/SOC Conference,<\/em> pp. 39-43, Arlington, USA, September 2001.<\/li>\n<li><strong> A. Fish<\/strong> and O. Yadid-Pecht \u201cCMOS Current\/Voltage Mode Winner-Take-All Circuit with Spatial Filtering\u201d, <em>Proc. IEEE International Symposium on Circuits and Systems,<\/em> vol. 2, pp. 636-639, Sydney, Australia, May 2001.<\/li>\n<\/ol>\n<ul style=\"text-align: justify\">\n<li><strong>Invited papers\/presentations<br \/>\n<\/strong><\/li>\n<\/ul>\n<ol style=\"text-align: justify\">\n<li>Levi, O. Keren and <strong>A. Fish<\/strong>, \u201cCPA Secured Data-Dependent Delay-Assignment Methodology\u201d, <em>to be presented at IEEE ISCAS<\/em>, Baltimore, May 2017.<\/li>\n<li>Avital, I. Levi, O. Keren and <strong>A. Fish<\/strong>, \"CMOS Based Gates for Blurring Power Information\", <em>to be presented at IEEE ISCAS,<\/em> Baltimore, May 2017.<\/li>\n<li>R. Giterman, A. Teman, P. Meinerzhagen, L. Atias, A. Burg and <strong>A. Fish<\/strong>,<br \/>\n\"Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications\", TCAS special session on Energy Efficient Circuits &amp; Systems, <em>IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>I. Levi, O. Keren and <strong>A. Fish<\/strong>, \"Data-Dependent Delays As a Barrier Against Power Attacks\", <em>IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>L. Atias, A. Teman, R. Giterman, P. Meinerzhagen and <strong>A. Fish<\/strong>, \u00a0\"Low-Voltage Radiation-Hardened 13T SRAM bitcell for Ultra-Low Power Space Applications\", <em>IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>M. Avital, H. Dagan, O. Keren and <strong>A. Fish<\/strong>, \"Randomized Multi-Topology Logic Against Differential Power Analysis\", <em>IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>M. Avital, H. Dagan, I. Levi, O. Keren and <strong>A. Fish<\/strong>, \"DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes\", <em>IEEE ISCAS<\/em>, Montreal, Canada, May 2016.<\/li>\n<li>A. Belenky, E. Artyomov, <strong>A. Fish<\/strong>, O. Yadid-Pecht, \u201cWide dynamic range (WDR) imaging\u201d, invited paper, <em>The Neuromorphic Engineer<\/em>, Vol. 1, Issue 1, p. 4., 2004.<\/li>\n<li><strong>A. Fish<\/strong>, V. Milirud and O. Yadid-Pecht, \u201cHigh-speed and high-precision current winner-take-all circuit\", <em>The Neuromorphic Engineer<\/em>, Vol. 2, Issue 2, p. 6, 2005.<\/li>\n<\/ol>\n<ul style=\"text-align: justify\">\n<li><strong>Lectures and Presentations<\/strong><\/li>\n<\/ul>\n<ol>\n<li style=\"text-align: justify\">\u201cEnergy-Efficient Memories, invited talk, Green Photonics symposium, Technion, March 2016.<\/li>\n<li style=\"text-align: justify\">\u201cAlternative Logic Families for Energy-Efficient, Fast and Secured Chip Design\u201d, invited talk, Green Photonics symposium, Berlin, March 2015.<\/li>\n<li style=\"text-align: justify\">\"Alternative Circuit Solutions\", Intel Labs, Portland, October, 2014.<\/li>\n<li style=\"text-align: justify\">\u201cHigh performance, low power and secured IC components\u201d, invited lecture, University of Freiburg, August 2014.<\/li>\n<li style=\"text-align: justify\">\u201cAlternative circuit level solutions for fast, energy- efficient and secured IC components\u201d, invited lecture, UC Louvain, August 2014.<\/li>\n<li style=\"text-align: justify\">\"Energy Efficient Dual Mode Logic\", invited lecture, UC Berkeley, October, 2012.<\/li>\n<li style=\"text-align: justify\">\u201cEnergy Efficient Nanoscaled VLSI chips\u201d, invited lecture, BGU energy initiative event.<\/li>\n<li style=\"text-align: justify\">\u201cLow voltage Logic and SRAM design\u201d, invited lecture, IBM, October 2010.<\/li>\n<li style=\"text-align: justify\">\u00a0\u201cDigital Low voltage Logic in the Era NaNoscale CMOS\u201d, invited lecture, Tel Aviv University, March 2010.<\/li>\n<li style=\"text-align: justify\">\u201cDigital Subthreshold Logic Design in the Era NaNoscale CMOS\u201d, \u00a0Invited for Chip Design Conference, Tel Aviv, November 2009.<\/li>\n<li style=\"text-align: justify\">\"Digital Subthreshold Logic Design - Motivation and Challenges\", invited lecture, Technion, December 2008.<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p>Conference papers 2018-2021 I. Stanger, N. Shavit, R. Taco, M. Lanuzza, A. Fish, \u201cLive Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths\u201d, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), hybrid N. Shavit, I. Stanger, R. Taco, M. Lanuzza, A. Fish, \u201cLive Demonstration: A 0.8V, 1.54 pJ \/ 940 MHz Dual &hellip; <a href=\"https:\/\/www.eng.biu.ac.il\/fishale\/publications\/conference-papers\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Conferences<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":25,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-246","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/246"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/comments?post=246"}],"version-history":[{"count":77,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/246\/revisions"}],"predecessor-version":[{"id":491,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/246\/revisions\/491"}],"up":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/25"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/media?parent=246"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}