{"id":242,"date":"2016-09-07T15:12:42","date_gmt":"2016-09-07T12:12:42","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/fishale\/?page_id=242"},"modified":"2021-08-03T11:49:53","modified_gmt":"2021-08-03T08:49:53","slug":"journals","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/fishale\/publications\/journals\/","title":{"rendered":"Journals"},"content":{"rendered":"

2017-2021<\/strong><\/p>\n

    \n
  1. Y. Weizman, R. Giterman, O. Chertkow, M. Vizentovski, I. Levi, I. Sever, I. Kehati, O. Keren, and A. Fish<\/strong>,\u00a0 \"Low-Cost Side-Channel Secure Standard 6T SRAM Based Memory with a 1% Area and less than 5% Latency and Power Overheads<\/a>\" - IEEE Access<\/em>, vol. 9, pp. 91764-91776, 2021<\/li>\n
  2. I. Stanger, N. Shavit, R. Taco, M. Lanuzza and A. Fish<\/strong>, \"Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths<\/a>\" in IEEE Transactions on Circuits and Systems II (TCAS-II)<\/em>, 2020<\/li>\n
  3. N. Shavit, I. Stanger, R. Taco, M. Lanuzza and A. Fish<\/strong>, \"A 0.8-V, 1.54-pJ\/940-MHz Dual-Mode Logic-Based 16\u00d716-b Booth Multiplier in 16-nm FinFET,<\/a>\" in IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 314-317, 2020<\/li>\n
  4. D. Zooker, O. Ohev Shalom, Y. Weizman, A. Fish<\/strong> and O. Keren, \"Toward Secured FPGA: Silicon Proven CLB With Reduced Information Leakage<\/a>\", in IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 146-149, 2020<\/li>\n
  5. R. Giterman, A. Shalom, A. Burg, A. Fish<\/strong>, A. Teman - \"A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET<\/a>\", in IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 110-113, 2020<\/li>\n
  6. A. Haran, E. Keren, D. David, N. Refaeli, R. Giterman, M. Assaf, L. Atias, A. Teman and A.<\/strong> Fish<\/strong>, \"Single Event Upset Tolerance Study of a Low Voltage 13T Radiation-Hardened SRAM Bitcell<\/a>,<\/a>\" in IEEE Transactions on Nuclear Science, <\/em>pp. 1-12, <\/em>2020<\/li>\n
  7. D. Zooker, M. Avital, Y. Weizman, A. Fish<\/strong> and O. Keren, \u201cSilicon Proven 1.8\u03bcm X 9.2\u03bcm 65- nm Digital Bit Generator for Hardware Security Applications,<\/a>\" in IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 66, no. 10, pp. 1713-1717, Oct. 2019.<\/li>\n
  8. R. Taco, I. Levi, M. Lanuzza and A. Fish<\/strong>,\u00a0 \"An 88-fJ\/40-MHz [0.4 V]\u20130.61-pJ\/1-GHz [0.9 V] Dual-Mode Logic 8 $\\times$ 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI<\/a>,\" in\u00a0IEEE Journal of Solid-State Circuits<\/em>, vol. 54, no. 2, pp. 560-568, Feb. 2019.<\/li>\n
  9. R. Giterman, O. Keren and A. Fish<\/strong>. \u201cA 7T Security Oriented SRAM Bitcell<\/a>\u201d. IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>. 1-1, 2018<\/li>\n
  10. R. Giterman, A. Fish<\/strong>, A. Burg and A. Teman, \u201cA 4-transistor nMOS-only logic-compatible gain-cell embedded DRAM with over 1.6-ms retention time at 700 mV in 28-nm FD-SOI<\/a>\u201d, IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 65, pp. 1245-1256, April 2018.<\/li>\n
  11. R. Giterman, A. Fish<\/strong>, N. Geuli, E. Mentovich, A. Burg and A. Teman, \u201cAn 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications<\/a>\u201d, IEEE Journal of Solid-State Circuits<\/em>, vol. 53, issue 7, pp. 2136-2148, July 2018.<\/li>\n
  12. R. Giterman, M. Vicentowski, I. Levi, Y. Weizman, O. Keren and A. Fish<\/strong>, \u201cLeakage Power Attack-Resilient Symmetrical 8T SRAM Cell<\/a>\u201d IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/em>, vol. 26, issue 10, pp. 2180-2184, October 2018.<\/li>\n
  13. U. Zangi, N. Feldman, T. Hadas, N. Dayag, J. Shor and A. Fish<\/strong>, \u201c0.45 v and 18 \u03bcA\/MHz MCU SOC with Advanced Adaptive Dynamic Voltage Control (ADVC)<\/a>\u201d, Journal of Low Power Electronics and Applications,<\/em> vol. 8, issue 2, 2018.<\/li>\n
  14. I. Levi, A. Fish<\/strong> and O. Keren. \u201dCPA secured data-dependent delay-assignment methodology<\/a>\u201d. IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/em>, 25<\/em> (2), 608-620, 2017.<\/li>\n
  15. I. Levi, N. Miller, E. Avni, O. Keren and A. Fish, <\/strong>\"A Survey of the Sensitivities of Security Oriented Flip-Flop Circuits<\/a>\u201d, IEEE Access<\/em>, vol. 5, pp. 24797\u00a0- 24809, November 2017.<\/li>\n
  16. I. Levi, A. Fish<\/strong> and O. Keren,\u00a0 \"Low Cost Pseudoasynchronous Circuit Design Style with Reduced Exploitable Side-Information<\/a>\", IEEE Transactions on VLSI systems<\/em>, vol. 99, pp. 1-14, October 2017.<\/li>\n
  17. R. Giterman, A. Fish<\/strong>, A. Burg and A. Teman, \u201cA 4-Transistor NMOS-only Logic-Compatible Gain-Cell Embedded DRAM with over 1.6ms Retention Time at 700mV in 28nm FD-SOI<\/a>\u201d, IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 99, pp. 1-14, October 2017.<\/li>\n
  18. A. Mordakhay, Y. Telepinsky, L. Klein, J. Shor and A. Fish, <\/strong>\u201cA Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory<\/a>\", IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 99, pp. 1-14, September 2017.<\/li>\n
  19. A. Kazimirsky, A. Teman and A. Fish, <\/strong>\u201cA 0.65V 500MHz Integrated Dynamic and Static RAM (iD-SRAM) for Error Tolerant Applications<\/a>,\u201d IEEE Transactions on VLSI systems<\/em>, vol. 25, issue 9, pp. 2411\u00a0-\u00a02418, 2017.<\/li>\n<\/ol>\n

    2015-2016<\/strong><\/p>\n

      \n
    1. E. Tadmor, D. Cohen, G. Yahav, G. Tennenholtz, G. Lehana, A. Lahav, A. Birman, A. Fenigstein and A. Fish<\/strong>, \"Development of a ToF Pixel with VOD Shutter Mechanism, High IR QE, 4 Storages & CDS<\/a>\", IEEE Transactions on Electron Devices<\/em>, vol. 63, issue 7, pp. 2892-2899, July 2016.<\/li>\n
    2. L. Moyal, I. Levi, A. Teman and A. Fish<\/strong>, \u201cSynthesis of Dual Mode Logic<\/a>\", Integration, the VLSI Journal, Elsevier<\/em>, vol 55<\/a>, pp. 246\u2013253, September 2016.<\/li>\n
    3. M. Avital, I. Levi, O. Keren and A. Fish<\/strong>, \"CMOS based Gates for Blurring Power Information<\/a>\", IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 63, issue 7, pp. 1033-1042, July 2016.<\/li>\n
    4. L. Atias, A. Teman, R. Giterman, P. Meinerzhagen and A. Fish<\/strong>, \"A Low-Voltage Radiation-Hardened 13T SRAM bitcell for Ultra-Low Power Space Applications<\/a>\", IEEE Transactions on VLSI systems<\/em>, vol. 24, issue 8, pp. 2622-2633, February 2016.<\/li>\n
    5. V. Yuzhaninov, I. Levi, and A. Fish<\/strong>, \"Design Flow and Characterization Methodology for Dual Mode Logic<\/a>\", IEEE Access<\/em>, vol. 3, pp. 3089-3101, January 2016.<\/li>\n
    6. N. Edri, P. Meinerzhagen, A. Teman, A. Burg, and A<\/strong>.<\/strong> Fish<\/strong>, \"Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAM<\/a>\", IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 63, issue 2, pp. 222-232, February 2016.<\/li>\n
    7. R. Taco, I. Levi, M. Lanuzza and A. Fish<\/strong>, \"Low Voltage Logic Circuits Exploiting Gate Level Dynamic Body Biasing in 28 nm UTBB FD-SOI<\/a>\", Solid State Electronics Journal<\/em>, Elsevier, vol. 117, pp. 185-192, March 2016.<\/li>\n
    8. E. Tadmor, A. Lahav, G. Yahav, A. Fish<\/strong> and D. Cohen, \u201cA Fast-Gated CMOS Image Sensor With a Vertical Over\ufb02ow Drain Shutter Mechanism<\/a>\u201d, IEEE Transactions on Electron Devices<\/em>, vol. 15, issue 7, pp. 3967-3972, July 2015.<\/li>\n
    9. I. Levi, O. Keren and A. Fish<\/strong>, \"Data-Dependent Delays as a Barrier Against Power Attacks<\/a>\", IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 62, issue 8, pp. 2069-2078, August 2015.<\/li>\n
    10. O. Chertkow,\u00a0A. Pescovsky, L. Atias and A. Fish<\/strong>, \"A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities<\/a>\", Journal of Low Power Electronics and Applications<\/em>, vol. 5, issue 2,\u00a0 pp. 130-150, June 2015.<\/li>\n
    11. O. Bass, A. Fish<\/strong> and D. Naveh, \u201cA Memristor as Multi-Bit Memory Feasibility Analysis<\/a>\u201d, special issue on memristors, Journal of Radioengineering<\/em>, vol. 24, issue 2, pp. 425-430, June 2015.<\/li>\n
    12. E. Tadmor, A. Nevet, G. Yahav, A. Fish<\/strong> and D. Cohen, \u201cDynamic Multispectral Imaging Using the Vertical Over\ufb02ow Drain Structure<\/a>\", IEEE Sensors<\/em>, vol. 15, issue 7, pp. 3967-3972, July 2015.<\/li>\n
    13. M. Avital, H. Dagan, O. Keren and A. Fish<\/strong>, \u201cRandomized Multi Topology Logic (RMTL) against Differential Power Analysis<\/a>\u201d, IEEE Transactions on VLSI systems<\/em>,\u00a0vol. 23, issue 4, pp. 702-711, April 2015.<\/li>\n
    14. R. Giterman, A. Teman, P. Meinerzhagen, L. Atias, A. Burg, and A. Fish<\/strong>, \u201cSingle-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications<\/a>\u201d, IEEE Transactions on VLSI systems<\/em>, vol. 24, issue 1, pp. 358-362,\u00a0February 2015.<\/li>\n
    15. M. Avital, H. Dagan, I. Levi, O. Keren and A. Fish<\/strong>, \u201cDPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-PowerPassiveRFIDTagsEmployingS-Boxes<\/a>\u201d, IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 62, issue 1, pp. 149-156, January 2015.<\/li>\n<\/ol>\n

      <\/p>\n

      2013-2014<\/strong><\/p>\n

        \n
      1. H. Dagan, A. Shapira, A. Teman, A. Mordakhay, S. Jameson, E. Pikhay, V. Dayan, Y. Roizin, E. Socher and A. Fish<\/strong>, \u201cA Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory<\/a>\u201d, IEEE Journal of Solid State Circuits<\/em>, vol. 49, issue 9, pp. 1942-1957, September 2014.<\/li>\n
      2. I. Levi, A. Albeck, A. Fish<\/strong> and S. Wimer, \u201cA Low Energy and High Performance DM2 Adder<\/a>\u201d, IEEE Transactions on circuits and systems \u2013 I<\/em>, vol. 61, issue 11, pp. 3175-3183, November 2014.<\/li>\n
      3. A. Teman, P. Meinerzhagen, R. Giterman, A. Fish<\/strong> and A. Burg, \u201cReplica Technique for Adaptive Refresh Timing of Gain Cell embedded DRAM<\/a>\", IEEE Transactions on Circuits and Systems II<\/em>, vol. 61, issue 4, pp. 259-263, April 2014.<\/li>\n
      4. I. Levi, A. Belenky and A. Fish<\/strong>, \u201cLogical Effort for CMOS Based Dual Mode Logic (DML) Gates<\/a>\"<\/em>, in\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/em>, vol. 22, no. 5, pp. 1042-1053, May 2014.<\/li>\n
      5. A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky and A. Fish<\/strong>, \u201cFull-Swing Gate Diffusion Input Logic \u2013case-study of low-power CLA Adder design<\/a>\u201d, Integration, The VLSI Journal<\/em>, Elsevier, vol. 47, issue 1, pp. 62-70, January 2014.<\/li>\n
      6. H. Dagan, A. Teman, E. Pikhay, V. Dayan, Y. Roizin and A. Fish<\/strong>, \u201cA Low-Power DCVSL-Like GIDL-Free Voltage DriverforLow-CostRFIDNonvolatileMemory<\/a>\u201d, IEEE Journal of Solid State Circuits<\/em>, vol. 48, issue 6, pp. 1497\u20131510, June 2013.<\/li>\n
      7. P. Meinerzhagen, A. Teman, A. Fish<\/strong> and A. Burg, \u201cImpact of body biasing on the retention time of gain-cell memories<\/a>\u201d, The Journal of Engineering<\/em>, vol. 1, issue 1, August 2013.<\/li>\n
      8. N. Krihely, S. Ben-Yaakov and A. Fish<\/strong>, \u201cEfficiency Optimization of Step-Down Switched Capacitor Converter for SubThreshold Applications<\/a>\u201d, IEEE Transactions on VLSI systems<\/em>, vol. 21, issue 12, pp. 2353\u20132357, December 2013.<\/li>\n
      9. I. Levi and A. Fish, <\/strong>\"Dual Mode Logic-Design for Energy Efficiency and High Performance<\/a>\", IEEE Access<\/em>, vol. 1, pp. 258-265, 2013.<\/li>\n
      10. O. Bass, A. Meiri, Z. Zalevsky and A. Fish<\/strong>, \u201dPhotonic XOR with inherent loss compensation mechanism for memory cell implementation in a standard nanoscale very large-scale integrated fabrication process<\/a>\u201d , Optics<\/em> Letters<\/em>, vol. 38, issue 9, pp. 1473-1475, May 2013.<\/li>\n
      11. P. Meinerzhagen, A. Teman, R. Giterman, A. Burg and A. Fish<\/strong>, \u201cExploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling<\/a>\u201d, Journal of Low Power Electronics and Applications<\/em>, vol. 3, issue 2, pp. 54-72, June 2013.<\/li>\n
      12. A. Teman, A. Mordakhay and A. Fish<\/strong>, \u201cFunctionality and Stability Analysis of a 400mV Quasi-Static RAM (QSRAM) Bitcell<\/a>\u201d, Microelectronics Journal<\/em>, Elsevier, vol. 44, issue 3, pp. 236-247, March 2013.<\/li>\n
      13. I. Levi, A. Kaizerman and A. Fish<\/strong>, \u201cLow Voltage Dual Mode Logic Model Analysis and Parameter Extraction<\/a>\u201d, Microelectronics Journal<\/em>, Elsevier, vol. 44, issue 6, pp. 553-560, June 2013.<\/li>\n
      14. S. D. Roy, X. Li, Y. Shoshan, A. Fish<\/strong> and O. Yadid-Pecht, \u201cHardware Implementation of a Digital Watermarking System for Video Authentication<\/a>\u201d, IEEE Transactions on Circuits and Systems for Video Technology<\/em>, vol. 23, issue 2, pp. 289-301, February 2013.<\/li>\n
      15. A. Spivak, A. Belenky, A. Fish<\/strong> and O. Yadid-Pecht, \u201cAnalog Encoding Voltage\u2014A Key to Ultra-Wide Dynamic Range and Low Power CMOS Image Sensor<\/a>\u201d, Journal of Low Power Electronics and Applications<\/em>, vol. 3, issue 1, pp. 27-53, March 2013.<\/li>\n
      16. A. Kaizerman, S. Fisher and A. Fish<\/strong>, \u201cSubthreshold Dual Mode Logic<\/a>\u201c, IEEE Transactions on VLSI systems<\/em>, vol. 21, issue 5, pp. 979-983, May 2013.<\/li>\n
      17. A. Spivak, A. Belenky, A. Fish<\/strong>, and O. Yadid-Pecht, \u201cAnalysis of Gated CMOS Image Sensor for Spatial Filtering<\/a>\u201d, IEEE Transactions on Electron Devices<\/em>, vol. 60, issue 1, pp. 305-313, January 2013.<\/li>\n<\/ol>\n

        <\/p>\n

        2011-2012<\/strong><\/p>\n

          \n
        1. A. Teman, A. Mordakhay, J. Mezhibovsky and A. Fish<\/strong>, \u201cA 40 nm Sub-Threshold 5T SRAM Bit Cell with Improved Read and Write Stability<\/a>\u201d, IEEE Transactions on Circuits and Systems II<\/em>, vol. 59, issue 12, pp. 873-877, December 2012.<\/li>\n
        2. A. Spivak, A. Teman, A. Belenky, O. Yadid-Pecht and A. Fish<\/strong>, \u201cLow-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel<\/a>\u201d, Sensors<\/em>, vol. 12, issue 8, pp. 10067-10085, July 2012.<\/li>\n
        3. A. Meiri, S. Tzur, Y. Cohen, O. Bass, A. Fish<\/strong> and Z. Zalevsky,\u00a0 \u201cMultilayer photonic logic gate integrated into microelectronic chip<\/a>\u201d, SPIE Journal of Nano Photonics<\/em>, vol. 6, issue 1, September 2012.<\/li>\n
        4. A. Teman, O. Yadid-Pecht and A. Fish<\/strong>, \u201cLeakage Reduction in Advanced Image Sensors Using an Improved AB2C Scheme<\/a>\u201d, IEEE Sensors<\/em>, Vol. 12, issue 4, pp. 773-784,\u00a0April 2012 (in the list of Top Accessed Articles, February 2012<\/strong>).<\/li>\n
        5. O. Yadid-Pecht, A. Fish<\/strong> and K. Roy, \u201cEditorial Special Issue on Low-Power Arrays<\/a>\u201d, IEEE Sensors<\/em>, Vol. 12, issue 4,\u00a0 pp. 717-719, April 2012.<\/li>\n
        6. A. Teman, L. Pergament, O. Cohen and A. Fish<\/strong>, \u201cA 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)<\/a>\u201d, IEEE Journal of Solid State Circuits<\/em>, vol. 46, issue 11, pp. 2713\u20132726, November 2011.<\/li>\n
        7. A. Teman, L. Pergament, O. Cohen and A. Fish<\/strong>, \u201cA Minimum Leakage Quasi-Static RAM Bitcell<\/a>\u201d, Journal of Low Power Electronics and Applications<\/em>, vol. 1, issue 1, pp. 204-218, June 2011.<\/li>\n
        8. A. Spivak, A. Belenky, A. Fish<\/strong> and O. Yadid-Pecht, \u201cA Wide-Dynamic-Range CMOS Image Sensor With Gating for Night Vision Systems<\/a>\u201d, IEEE Transactions on Circuits and Systems II<\/em>, vol. 58, issue 2, pp. 85-89, February 2011 (in the list of Top Accessed Articles, March 2011).<\/li>\n
        9. A. Spivak, A. Teman, A. Belenky, O. Yadid-Pecht and A. Fish<\/strong>, \u201cPower-Performance Tradeoffs in Wide Dynamic Range Image Sensors with Multiple Reset Approach<\/a>\u201d, Journal of Low Power Electronics and Applications<\/em>, vol. 1, issue 1, pp. 59-76, June 2011.<\/li>\n<\/ol>\n

          <\/p>\n

          2007-2010<\/strong><\/p>\n

            \n
          1. A. Teman, O.Yadid-Pecht and A. Fish<\/strong>, \u201cLarge VLSI Arrays \u2013 Power and Architectural Perspectives<\/a>\u201d, International Journal Information Technologies and Knowledge<\/em> (IJ ITK), vol. 4, issue 1, pp. 76-88, November 2010.<\/li>\n
          2. A. Spivak, A. Belenky, A. Fish<\/strong> and O. Yadid-Pecht, \u201cWide-Dynamic-Range CMOS Image Sensors\u2014Comparative Performance Analysis<\/a>\u201d, IEEE Transactions on Electron Devices<\/em>, vol. 56, issue 11, pp. 2446-2461 , November 2009.<\/li>\n
          3. A. Belenky, A. Fish<\/strong>, A. Spivak and O. Yadid-Pecht, \u201cA Snapshot CMOS Image Sensor With Extended Dynamic Range<\/a>\u201d, IEEE Sensors Journal<\/em>, vol. 9, issue 2, pp. 103-111, Feb 2009.<\/li>\n
          4. X. Li, Y. Shoshan, A. Fish<\/strong>, G. A. Jullien and O. Yadid-Pecht, \u201cHardware Implementations of Video Watermarking<\/a>\u201d, International Journal on Information Technologies and Knowledge<\/em>, vol. 3, issue 2, pp. 103-120, November 2009.<\/li>\n
          5. M. Beiderman, T. Tam, A. Fish<\/strong>, G. A. Jullien and O. Yadid-Pecht, \u201cA Low-Light CMOS Contact Imager With an Emission Filter for Biosensing Applications<\/a>\u201d, IEEE Transactions on Biomedical Circuits and Systems<\/em>, vol. 2, issue 3, pp. 193-203, September 2008.<\/li>\n
          6. A. Belenky, A. Fish<\/strong>, A. Spivak, and O. Yadid-Pecht, \u201cGlobal Shutter CMOS Image Sensor With Wide Dynamic Range<\/a>\u201d, IEEE Transactions on Circuits and Systems II<\/em>, vol. 54, issue 12, pp. 1032-1036, December 2007.<\/li>\n
          7. Y. Shoshan, A. Fish<\/strong>, X. Li, G. A. Jullien and O. Yadid-Pecht, \u201cVLSI Watermark Implementations and Applications<\/a>\u201d, International Journal on Information Technologies and Knowledge<\/em>, vol. 2, issue 4, pp. 379-386, November 2008.<\/li>\n
          8. E. Artemov, A. Fish<\/strong> and O. Yadid-Pecht, \u201cImage sensors for Security and Medical Applications<\/a>\u201d, International Journal on Information Theory and Applications<\/em>, vol. 14, issue 2, pp. 114-127, November 2007.<\/li>\n
          9. A. Fish<\/strong>, L. Sudakov-Boresha and O. Yadid-Pecht, \u201cLow-power Tracking Image Sensor based on biological models of attention<\/a>\u201d, International Journal on Information Theory and Applications<\/em>, vol. 14, issue 2, pp. 103-114, November 2007.<\/li>\n<\/ol>\n

            <\/p>\n

            2002-2006<\/strong><\/p>\n

              \n
            1. A. Fish<\/strong>, S. Hamami and O. Yadid-Pecht, \u201cCMOS Image Sensors with Self-Power Generation Capability<\/a>\u201d, IEEE Transactions on Circuits and Systems II<\/em>, vol. 53, issue 11, pp. 1210-1214, November 2006.<\/li>\n
            2. A. Fish<\/strong>, A. Belenky and O. Yadid-Pecht, \u201cWide Dynamic Range Snapshot APS for Ultra Low-Power Applications<\/a>\", IEEE Transactions on Circuits and Systems II<\/em>, vol. 52, issue 11, pp. 729-733, November 2005.<\/li>\n
            3. A. Fish<\/strong> and O. Yadid-Pecht, \u201cBottleneck Problem Solution using Biological Models of Attention in high resolution tracking sensors<\/a>\u201d, International Journal on Information Theories and Applications<\/em>, vol. 12, pp. 29-35, November 2005 (Young investigator award for the best paper).<\/li>\n
            4. A. Fish<\/strong>, V. Milirud and O. Yadid-Pecht, \u201cHigh-Speed and High-Precision Current Winner-Take-All Circuit<\/a>\u201d, IEEE Transactions on Circuits and Systems II<\/em>, vol. 52, no. 3, pp. 131-135, March 2005.<\/li>\n
            5. S. Diller, A. Fish<\/strong> and O. Yadid-Pecht, \u201cAdvanced output chains for CMOS image sensors based on an active column sensor approach\u2014a detailed comparison<\/a>\u201d, Sensors & Actuators A: Physical<\/em>, vol. 116, issue 2, pp. 304-311, October 2004.<\/li>\n
            6. A. Fish<\/strong>, D. Akselrod and O. Yadid-Pecht, \"High Precision Image Centroid Computation via an Adaptive K-Winner-Take-all Circuit in Conjunction with a Dynamic Element Matching Algorithm for Star Tracking Applications<\/a>\", Analog Integrated Circuits and Signal Processing journal<\/em>, Vol. 39, issue 3, pp. 251-266, June 2004.<\/li>\n
            7. A. Fish<\/strong> and O. Yadid Pecht, \u201cAdaptive thresholding for visual attention and tracking systems<\/a>\u201d, Optical Engineering<\/em>, vol. 43, issue 6, pp. 1278-1279, June 2004.<\/li>\n
            8. A. Belenky, A. Fish<\/strong>, S. Hamami, V. Milrud and O. Yadid-Pecht, \u201cMethod for expanding the dynamic range of the readout integration circuits for uncooled microbolometer sensors<\/a>\u201d, Optical Engineering,<\/em> vol. 43, issue 6, pp.1274-1275, June 2004.<\/li>\n
            9. A. Fish<\/strong>, D. Turchin and O. Yadid-Pecht, \u201dAn APS With 2-D Winner-Take-All Selection Employing Adaptive Spatial Filtering and False Alarm Reductio<\/a>n\u201d, IEEE Transactions on Electron Devices<\/em>, Special Issue on Image Sensors, vol. 50, issue 1, pp. 159-165, January 2003.<\/li>\n
            10. A. Morgenshtein, A. Fish<\/strong> and I. A. Wagner, \"Gate-Diffusion Input (GDI) \u2013 A power-efficient method for digital combinatorial circuits<\/a> \"<\/a>, IEEE Transactions on VLSI systems<\/em>, vol. 10, issue 5, pp. 566-581, October 2002.<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

              2017-2021 Y. Weizman, R. Giterman, O. Chertkow, M. Vizentovski, I. Levi, I. Sever, I. Kehati, O. Keren, and A. Fish,\u00a0 “Low-Cost Side-Channel Secure Standard 6T SRAM Based Memory with a 1% Area and less than 5% Latency and Power Overheads” – IEEE Access, vol. 9, pp. 91764-91776, 2021 I. Stanger, N. Shavit, R. Taco, M. … Continue reading Journals<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":25,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-242","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/242"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/comments?post=242"}],"version-history":[{"count":149,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/242\/revisions"}],"predecessor-version":[{"id":605,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/242\/revisions\/605"}],"up":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/25"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/media?parent=242"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}