{"id":10,"date":"2012-10-16T16:21:46","date_gmt":"2012-10-16T14:21:46","guid":{"rendered":"http:\/\/www.eng.biu.ac.il\/fishale\/?page_id=10"},"modified":"2022-05-03T17:06:07","modified_gmt":"2022-05-03T14:06:07","slug":"patents","status":"publish","type":"page","link":"https:\/\/www.eng.biu.ac.il\/fishale\/patents\/","title":{"rendered":"Patents"},"content":{"rendered":"

\n

Granted<\/strong><\/h4>\n
    \n
  1. A. Fish<\/strong>, O. Keren, Y. Weizman and M. Elkoni, \u201cInformation Redistribution to reduce side channel leakage\u201d, US Patent No. 11,321,460, granted May 2022.<\/li>\n
  2. A. Teman, A. Fish<\/strong>, R. Giterman and A. Shalom, \"Embedded Dynamic Memory in FinFET Technology\", U.S. Patent No: 11,127,455, granted, Sep.21, 2021.<\/li>\n
  3. I. Levi, O. Keren and A. Fish<\/strong>, \"Pseudo-Asynchronous digital circuit design\",\u00a0 U.S. Patent No: 11,023,632 , granted, June 1, 2021.<\/li>\n
  4. R. Giterman, L. Atias, A. Teman and A. Fish<\/strong>, \"Complementary Dual-modular Redundancy Memory cell\", US patent No: 10,991,421 granted, April 27, 2021.<\/li>\n
  5. M. Avital, I. Levi, O. Keren and A. Fish<\/strong>, \u201cRandomized Logic against side channel attacks\u201d, US patent no. 10,951,39 granted, Mar. 16, 2021.<\/li>\n
  6. I. Levi, O. Keren, and A. Fish<\/strong>, \"Pseudo-asynchronous digital circuit design\". U.S. Patent No: 10,572,619, granted Feb. 25, 2020.<\/li>\n
  7. I. Levi, O. Keren and A. Fish<\/strong>, \"Data-dependent delay circuits\", US patent No: US 10,521,530, Granted December 2019.<\/li>\n
  8. R. Giterman, A. Teman, E. Mentovich, N. Geuli and A. Fish<\/strong>, \u201cHigh Density Memory Macro\u201d, US patent No: US 10,497,410, granted December 2019.<\/li>\n
  9. M. Avital, H. Dagan, O. Keren and A. Fish<\/strong>, \"Multi-Topology Logic Gates\", US patent No: 10,169,617, granted January 2019.<\/li>\n
  10. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and\u00a0A. Fish<\/strong>,\u00a0<\/strong>\"Transistor gain cell with feedback\", US patent No: 10,002,660, granted June 2018.<\/li>\n
  11. R. Giterman, A. Teman, P. Meinerzhagen, A. Burg and\u00a0A. Fish<\/strong>,\u00a0<\/strong>\"Transistor gain cell with feedback\", US patent No: 9,691,445, granted June 2017, EP 3138101 Granted Sep. 2019; IL \u00a0248633, Granted May 2019<\/li>\n
  12. A. Fish<\/strong>, A. Kaizerman, I. Levi and S. Fisher, \u201cDesign of Dual mode logic circuits\u201d, US patent No: 9,430,598, granted August 2016.<\/li>\n
  13. A. Fish<\/strong>, A. Kaizerman, I. Levy and S. Fisher, \"Device and method for dual-mode logic\", US patent No: 8,901,965, granted December 2014.<\/li>\n
  14. A. Teman, L. Pergament, O. Cohen and A. Fish<\/strong>, \u201cUltra low power memory cell with a supply feedback loop configured for minimal leakage operation\u201d, US patent No: 8,773,895, granted July 2014.<\/li>\n
  15. A. Teman, L. Pergament, O. Cohen and A. Fish<\/strong>, \u201cUltra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation\u201d, US patent No: 8,531,873, granted September 2013.<\/li>\n
  16. O. Yadid-Pecht, Y. Shoshan and A. Fish<\/strong>, \u201dDigital Watermarking CMOS Sensor\u201d, US patent No: 8,280,098, granted October 2012.<\/li>\n
  17. E. Artyomov, A. Fish<\/strong>, B. Maliatski and O. Yadid-Pecht, \u201cConfigurable ASIC-based sensing circuit\u201d, EP patent No: 1,946,229, Granted May 2012.<\/li>\n
  18. A. Fish <\/strong>and A. Morgenshtein,\u00a0 \u201cLogic circuit and method of logic circuit design\u201d, US Patent No: 8,188,767, granted May 2012.<\/li>\n
  19. A. Morgenshtein, A. Fish <\/strong>and I.A. Wagner, \u201cLogic circuit and method of logic circuit design\u201d US Patent No: 8,161,427, granted April 2012.<\/li>\n
  20. A. Fish <\/strong>and A. Morgenshtein, \u201cLogic circuit and method of logic circuit design\u201d, US Patent No: 8,004,316, granted August 2011.<\/li>\n
  21. A. Belenky, A. Fish <\/strong>and O. Yadid-Pecht, \u201cOptical Pixel and Image Sensor\u201d, provisional application, US Patent No: 7,990,451, granted August 2011.<\/li>\n
  22. A. Morgenshtein,\u00a0A. Fish\u00a0<\/strong>and I.A. Wagner, \u201cLogic circuit and method of logic circuit design\" US Patent No: 7,716,625, granted May 2010.<\/li>\n
  23. A. Morgenshtein, A. Fish<\/strong>, I.A. Wagner, \"Logic circuit and method of logic circuit design\", US patent\u00a0 No. 7, 345, 511, granted March 2008.<\/li>\n<\/ol>\n

    Applications<\/strong><\/h4>\n
      \n
    1. R. Giterman, I. Levi, O. Keren, and\u00a0A. Fish<\/strong>, \u201cSecured memory\u201d,\u00a0PCT application No: PCT\/IL2018\/051338, US 16\/769,664, December 2018<\/li>\n
    2. A. Fish<\/strong>, M. Avital, A. Mordakhay, Y. Weizman and O. Keren, \u201cCompact Bit Generator\u201d, Application No.: US 16\/224,869, December 2018<\/li>\n
    3. A. Fish<\/strong>, Z. Zalevsky, A. Meiri and O.Bass, \"Integrated circuit with photonic elements\", PCT application No: PCT\/IL2013\/050765, March 2014<\/li>\n
    4. A. Teman, L. Pergament, O. Cohen\u00a0 and A. Fish<\/strong>, \u201cUltra low power memory cell with a supply feedback loop configured for minimal leakage operation\u201d, US application No: US 13103093, November 2012<\/li>\n
    5. A. Fish<\/strong> and A. Morgenshtein, \u201cLogic circuit and method of logic circuit design\u201d, US application No: US 13439949, August 2012<\/li>\n
    6. A. Morgenshtein, A. Fish <\/strong>and I.A. Wagner, \"Logic circuit and method of logic circuit design\", US application No: US 13364355, May 2012<\/li>\n
    7. A. Belenky, A. Fish<\/strong>, O. Yadid-Pecht and D. Ofer, \"Optical pixel and image sensor\", PCT application No: PCT\/IL2010\/000054, July 2010<\/li>\n
    8. E. Artyomov, A. Fish<\/strong>, B. Maliatski and O. Yadid-Pecht, \u201cConfigurable ASIC-based sensing circuit\u201d, US application No: US11991849, April 2009<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

      Granted A. Fish, O. Keren, Y. Weizman and M. Elkoni, \u201cInformation Redistribution to reduce side channel leakage\u201d, US Patent No. 11,321,460, granted May 2022. A. Teman, A. Fish, R. Giterman and A. Shalom, “Embedded Dynamic Memory in FinFET Technology”, U.S. Patent No: 11,127,455, granted, Sep.21, 2021. I. Levi, O. Keren and A. Fish, “Pseudo-Asynchronous digital … Continue reading Patents<\/span> →<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-10","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/10"}],"collection":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/comments?post=10"}],"version-history":[{"count":45,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/10\/revisions"}],"predecessor-version":[{"id":621,"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/pages\/10\/revisions\/621"}],"wp:attachment":[{"href":"https:\/\/www.eng.biu.ac.il\/fishale\/wp-json\/wp\/v2\/media?parent=10"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}