HiPer Consortium Event Schedule

Wednesday, May 24th  2017

08:30-15:30

Faculty of Engineering, Bar-Ilan University

Schedule

08:30 – 09:30 Registration and Coffee
09:30 – 09:45 Welcome and HiPer 3rd Year Overview

  • Ilan Peled
  • Rafi Retter
09:45 – 10:30 Keynote:

On-Chip Memory: From Bulk-CMOS to Multi-gate Devices and Magnets

  • Prof. Kaushik Roy, Purdue University
10:30 – 11:30 Expert Panel: VLSI Technologies in the Twilight of Moore’s Law and Beyond

  • Prof. Kaushik Roy, Purdue University
  • Dan Kochpatcharin, TSMC
  • Marco Casale Rossi, Synopsys
  • Ofer Bustin, Mellanox
11:30 – 12:00 SoC Lab @ BIU

  • Yonatan Shoshan,  EnICS
12:00 – 12:20 SoC1 + DAFNA Demonstrations
12:20 – 13:30 Lunch
Lectures by Consortium members: Three years major achievements
13:30 – 13:50 Optimal Generation of Multiplier Arrays

  • Udi Kara, Satixfy
13:50 – 14:10 DAFNA - Scaling GC-eDRAM down to 28nm

  • Robert Giterman,  EnICS Labs
14:10 – 14:30 Multicore Challenges & Research Directions

  • Alon Ya’akov, CEVA
14:30 – 14:50 Consortium Achievements in VLSI Verification

  • Noam Meser, CEVA
14:50 – 15:10 Utilizing Vector Processor DSP Architecture Features for TC Application Speedup

  • Shlomo Greenberg, BGU