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Cadence University Program Member
The aim of the Cadence® Academic Network is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. This knowledge network among selected universities, research institutes, industry advisers, and Cadence was established in 2007 to facilitate the sharing of technology expertise in the areas of verification, design, and implementation of microelectronic systems. We work individually with academic institutions based on their requirements and their profile.
The Cadence Academic Network consists of the following categories:
- Academic Partnerships – Fostering collaboration between academia and industry
- University Software Program – Providing educational institutes easy access to Cadence technology and enabling them to make sophisticated use of these technologies
- University Recruiting – From internships to co-operative education to job opportunities, Cadence offers post-college graduates the opportunity to be part of a winning team that’s transforming the electronic design automation (EDA) industry.
Information can also be found on the Cadence Academic Network web page.
Microchips – the future is here
The SoC lab, operating under the auspices of the EnICS Impact Center at Bar-Ilan’s Faculty of Engineering, spearheading chip design research in Israel.
An Israeli consortium called HiPer (High Performance System-on-Chip Design) was jointly established with Israeli chip companies and academic groups focusing on chip design research. Spearheading this venture is the Emerging Nanoscaled Integrated Circuits & Systems (EnICS) Impact Center at BIU, comprising of four BIU researchers – Prof. Alex Fish, Prof. Yossi Shor, Dr. Osnat Keren, and Dr. Teman. The objective of HiPer is to develop better chips, in terms of energy-efficiency, performance, cost, security, etc. The consortium established a lab for developing systems-on-chip (SoC Lab), within the EnICS Impact Center. “We decided to establish an Israeli VLSI expertise center, in order to bridge the gap between innovation and product, connecting the point of idea to the point of realization,” explains Dr. Teman. “We aim to facilitate a smooth transition from academia and industry, and become a platform for chip-related innovation, which can be translated into industrial applications. This is the great advantage of academic research: we are not dictated to by the market, and are able to study and develop innovative solutions without risking investors’ interests.”
In 2016, three years after the HiPer consortium was launched, the SoC Lab completed its first chip. “It was a highly advanced chip, designed in 28 nanometer technology. After undergoing comprehensive post-silicon testing, the chip has been proven to tick every required box. This project proved that we can produce one compound industrial chip, at a much lesser cost than the $50m the industry would have had to pay,” recalls Teman. “Following this successful pilot, the HiPer consortium was granted a second term (5-years total), and we are now developing a second chip, incorporating innovative developments courtesy of EnICS Labs. This new chip is produced using a highly advanced technology: 16 nanometers FinFET.” Following these developments, a proposal was submitted for the establishment of a new consortium, titled GenPro, which will focus on developing a Made-in-Israel processor. Last April, the consortium was approved by the Israel Innovation Authority, and will be launched in September 2018. BIU’s SoC Lab will be used as the consortium’s activity hub, leading the innovative development and integration work.
Thanks to the Cadence Academic Network, our labs have been able to develop this advance technology by using in our research the following Cadence tools:
Area |
Category |
Tool |
System Design & Verification |
Emulation | Palladium |
| Planning and management | vManager | |
| Simulation and Test bench | Incisive | |
| Specman | ||
| Verification IP | ||
| Debug | SimVision | |
Digital Design and Sign off |
Block Implementation | Innovus |
| Virtouso | ||
| Logic Equivalence | Conformal LEC | |
| Hierarchical Design and Floor planning | Innovus | |
| Virtouso | ||
| SDC and CDC | Conformal Constraint Designer | |
| Synthesis | Genus | |
| Silicon Sign off and Verification | Quantus Extraction | |
| Tempus Timing Verification | ||
| Power Integrity | Voltus | |
| LVS/DRC | Pegasus | |
Custom/Analog |
Circuit Design | Virtuoso |
| Layout Verification | Virtuoso | |
| Quantus Extraction | ||
| Circuit Simulation | Spectre | |
| Library Characterization | Liberate |
As an example of our successful work, this past June, Dr. Adam Teman conducted a live demonstration of the chip he designed in the framework of the HiPer consortium. The demonstration was held in Florence, Italy, during the ISCAS international conference, the biggest annual conference on chips and circuits.
“This is all a part of the EnICS team’s vision, aspiring for international success both in research and teaching, and working together to lead the Israeli chip industry to a promising future”.
EnICS - Transforming Ideation to Creation
Some of our recent chips
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| BEER | CAMEL | SPACE IMAGER | TRPLA |
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| PATHFINDER | GREENBELT2 | DigIL | SoC1 |
Contact information:
Clara Korn
Academic Assistant
EnICS - Emerging Nanoscaled Circuits and Systems Labs
Faculty of Engineering
Bar-Ilan University
Tel.: +972-3-7384654
Email: enics.lab@biu.ac.il
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