Shmuel Wimer is a VLSI expert, having thirty-two years of industrial experience, and another eight years in academia. He is an associate professor with the Engineering Faculty of Bar-Ilan University (BIU). From 2011 to 2015 he was a visiting associate professor with the Electrical Engineering Faculty at the Technion - Israel Institute of Technology. He holds BSc degree (1977) and MSc degree (1981) in Mathematics from Tel-Aviv University (TAU), and DSc degree in Electrical Engineering (1988) from the Technion. His research interests include VLSI circuits and systems design optimization, VLSI computational aspects, and combinatorial optimization.

Prior to joining the academia he worked at Intel (1999-2009), where he was a principal engineer and a group leader. He initiated, developed and managed the technology and design flow of migrating the hard IP of Intel’s mobile processors across the process technology road-map (a.k.a. “Tick-Tock”), from 130nm node (“Banias”) up to 45nm node (“Penryn”), and participated in the migration of the 32nm node (“Westmere”) and 22nm node (“Ivy-Bridge”).

Prior to Intel he was with Sagantec Israel (1997-1999) as a general and development manager, working on algorithms and tools for automatic layout migration. He was the founder and manger of a VLSI EDA company microCAD (1994-1997) that was later acquired by Sagantec. He was a research staff member with the IBM R&D center in Israel (1985-1993), where he was a project leader, group and program manager, working on the development and implementation of algorithms and CAD tools for physical layout. At IBM he also managed a circuit and layout design team. He was with National Semiconductor Israel (1981-1985), working as a VLSI CAD engineer and project leader, developing algorithms and CAD tools for logic optimization, RTL simulation, and floorplanning. Following his graduation, he worked at the Israel Aerospace Industry (IAI) (1977-1981) as an aeronautics and CAD engineer, where he developed software and CAD tools for flight simulations, trajectory optimization, and computer graphics.